Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
8.0
Bus Interface
This section provides an overview of Bus operations. The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of
all in-system read, write, and erase operations through the system bus. All bus cycles
to or from the flash memory conform to standard microprocessor bus cycles. Table 16
summarizes the necessary states of each control signal for different modes of
operations.
Table 16: Bus Operations
STS
(Default
Mode)
(1)
(2)
(2)
(3)
15:0
Mode
RP#
CE
OE#
WE#
V
DQ
Notes
x
PEN
Async., Status, Query and
Identifier Reads
V
Enabled
V
V
V
X
D
OUT
High Z
4,6
IH
IL
IH
Output Disable
Standby
V
V
Enabled
Disabled
X
V
X
X
X
X
High Z
High Z
High Z
High Z
High Z
High Z
High Z
—
—
IH
IH
IH
IH
X
X
Reset/Power-down
Command Writes
Array Writes
V
X
X
—
IL
IH
IH
V
V
Enabled
Enabled
V
V
D
IN
6,7
5,8
IH
IH
IL
IL
V
V
V
X
V
IL
PENH
Notes:
1.
2.
3.
4.
5.
6.
See Table 17 for valid CE configurations.
x
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
DQ refers to DQ[7:0] when BYTE# is low and DQ[15:0] if BYTE# is high.
Refer to DC characteristics. When VPEN ≤ V
, memory contents can be read but not altered.
PENLK
X should be V or V for the control pins and V
or V
for V
. For outputs, X should be V or V
.
OH
IL
IH
PENLK
PENH
PEN
OL
In default mode, STS is V when the WSM is executing internal block erase, program, or a lock-bit configuration
OL
algorithm. It is V
(pulled up by an external pull up resistance ≈ 10k) when the WSM is not busy, in block erase suspend
OH
mode (with programming inactive), program suspend mode, or reset power-down mode.
See Section 11.0, “Device Command Codes” on page 47 for valid DIN (user commands) during a Write
operation.
7.
8.
Array writes are either program or erase operations.
Table 17: Chip Enable Truth Table for 32-, 64-, 128-Mb
CE2
CE1
CE0
DEVICE
V
V
V
V
V
V
V
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
IL
IL
IL
IL
V
IL
IH
V
V
IL
IH
IH
IL
V
V
IL
IH
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
V
IL
IH
V
V
V
IH
IH
IL
V
IH
Note: For single-chip applications, CE2 and CE1 can be connected to VSS.
Datasheet
30
May 2009
208032-01
NUMONYX [ NUMONYX B.V ]
