290701-18 参数 Datasheet PDF下载

Numonyx™ Wireless Flash Memory (W18)

Table 31: Read Configuration Register Descriptions (Sheet 2 of 2)

Bit

3

Name

BW

Burst Wrap

BL[2:0]

Burst Length

Description

1

0 = Wrap bursts within burst length set by CR[2:0]

1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)

001

010

011

111

=

=

=

=

4-Word Burst

8-Word Burst

16-Word Burst

Continuous Burst (Default)

Notes

2-0

4

Notes:

1.

Undocumented combinations of bits are reserved by Numonyx for future implementations.

2.

Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status Register

and configuration reads support single read cycles. RCR[15]=1 disables configuration set by RCR[14:0].

3.

Data is not ready when WAIT is asserted.

4.

Set the synchronous burst length. In asynchronous page mode, the page size equals four words.

5.

Set all reserved Read Configuration Register bits to zero.

6.

Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010),

data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported.

14.1

Read Mode (RCR[15])

All partitions support two high-performance read configurations: synchronous burst

mode and asynchronous page mode (default). RCR[15] sets the read configuration to

one of these modes.

Status register, query, and identifier modes support only asynchronous and single-

synchronous read operations.

14.2

First Access Latency Count (RCR[13:11])

The First Access Latency Count (RCR[13:11]) configuration tells the device how many

clocks must elapse from ADV# de-assertion (V

IH

) before the first data word should be

driven onto its data pins. The input clock frequency determines this value. See

for latency values.

shows data output latency from ADV# assertion for different latencies. Refer

to

for Latency Code Settings.

Figure 36: First Access Latency Configuration

CLK [C]

Address [A]

Valid

Address

ADV# [V]

D[15:0] [Q]

D[15:0] [Q]

Code 2

Code 3

Code 4

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

D[15:0] [Q]

D[15:0] [Q]

Note:

)

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Code 5

Valid

Output

Valid

Output

Valid

Output

Other First Access Latency Configuration settings are reserved.

November 2007

Order Number: 290701-18

Datasheet

79