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290701-18 参数 Datasheet PDF下载

290701-18图片预览
型号: 290701-18
PDF下载: 下载PDF文件 查看货源
内容描述: 恒忆无线闪存( W18 ) [Numonyx Wireless Flash Memory (W18)]
分类和应用: 闪存无线
文件页数/大小: 102 页 / 1372 K
品牌: NUMONYX [ NUMONYX B.V ]
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Numonyx™ Wireless Flash Memory (W18)  
Figure 39: Data Output Configuration with WAIT Signal Delay  
CLK [C]  
WAIT (CR.8 = 1)  
Note 1  
Note 1  
tCHQV  
WAIT (CR.8 = 0)  
1 CLK  
Data Hold  
Valid  
Output  
Valid  
Output  
Valid  
Output  
DQ15-0 [Q]  
WAIT (CR.8 = 0)  
tCHTL/H  
Note 1  
Note 1  
tCHQV  
WAIT (CR.8 = 1)  
2 CLK  
Valid  
Output  
Valid  
Output  
DQ15-0 [Q]  
Data Hold  
Note: WAIT shown asserted high (RCR[10]=1).  
14.6  
WAIT Delay (RCR[8])  
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all  
synchronous read-array modes. Its setting depends on the system and CPU  
characteristics. The WAIT can be asserted either during, or one data cycle before, a  
valid output.  
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-, 8-, 16-, or  
continuous-word burst mode, an output delay may occur when a burst sequence  
crosses its first device-row boundary (16-word boundary). If the burst start address is  
4-word boundary aligned, the delay does not occur. If the start address is misaligned to  
a 4-word boundary, the delay occurs once per burst-mode read sequence. The WAIT  
signal informs the system of this delay.  
14.7  
Burst Sequence (RCR[7])  
The burst sequence specifies the synchronous-burst mode data order (see Table 35,  
“Sequence and Burst Length” on page 84). When operating in a linear burst mode,  
either 4-, 8-, or 16-word burst length with the burst wrap bit (RCR[3]) set, or in  
continuous burst mode, the device may incur an output delay when the burst sequence  
crosses the first 16-word boundary. (See Figure 37, “Word Boundary” on page 80 for  
word boundary description.) This depends on the starting address. If the starting  
address is aligned to a 4-word boundary, there is no delay. If the starting address is the  
end of a 4-word boundary, the output delay is one clock cycle less than the First Access  
Latency Count; this is the worst-case delay. The delay takes place only once, and only  
if the burst sequence crosses a 16-word boundary. The WAIT pin informs the system of  
this delay. For timing diagrams of WAIT functionality, see these figures:  
Figure 9, “Single Synchronous Read-Array Operation Waveform” on page 32  
Figure 10, “Synchronous 4-Word Burst Read Operation Waveform” on page 33  
Figure 11, “WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform”  
on page 34  
November 2007  
Order Number: 290701-18  
Datasheet  
83  
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