Numonyx™ Wireless Flash Memory (W18)
14.0
Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The Read Configuration
Register data is placed on the lower 16 bits of the address bus (A[15:0]) during both
bus cycles. The Set Read Configuration Register command is written along with the
configuration data (on the address bus). This is followed by a second write that
confirms the operation and again presents the Read Configuration Register data on the
address bus. The Read Configuration Register data is latched on the rising edge of
ADV#, CE#, or WE# (whichever occurs first). This command functions independently of
the applied V
PP
voltage. After executing this command, the device returns to read-array
mode. The Read Configuration Register’s contents can be examined by writing the Read
Identifier command and then reading location 05h. See
and
Table 30: Read Configuration Register Summary
Data Output Config
WAIT Polarity
WAIT Config
Clock Config
First Access Latency
Count
Burst Wrap
Read Mode
Burst Seq
Res’d
Res’d
Res’d
Burst Length
RM
15
R
14
LC2
13
LC1
12
LC0
11
WT
10
DOC
9
WC
8
BS
7
CC
6
R
5
R
4
BW
3
BL2
2
BL1
1
BL0
0
Table 31: Read Configuration Register Descriptions (Sheet 1 of 2)
Bit
15
14
13-11
Name
RM
Read Mode
R
LC[2:0]
First Access Latency Count
WT
WAIT Signal Polarity
DOC
Data Output Configuration
WC WAIT Configuration
BS
Burst Sequence
CC
Clock Configuration
R
R
Description
1
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
Reserved
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
Notes
2
5
6
10
9
8
7
6
5
4
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
1 = Linear Burst Order (Default)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
Reserved
Reserved
3
6
6
5
5
Datasheet
78
November 2007
Order Number: 290701-18
NUMONYX [ NUMONYX B.V ]
