Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time
(Figure 4 )
CMOS/TTL High-to-Low Transition Time
(Figure 4 )
Receiver Input Strobe Position for Bit 0
(Figure 18 )
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5)
(Figure 19 )
RxCLK OUT Period
(Figure 8)
RxCLK OUT High Time
(Figure 8 )
RxCLK OUT Low Time
(Figure 8)
RxOUT Setup to RxCLK OUT
(Figure 8 )
RxOUT Hold to RxCLK OUT
(Figure 8 )
Receiver Phase Lock Loop Set
(Figure 12 )
Receiver Power Down Delay
(Figure 16 )
f = 65 MHz
f = 65 MHz
f = 65 MHz
f = 65 MHz
f = 65 MHz
f = 65 MHz
0.7
2.9
5.1
7.3
9.5
11.7
13.9
400
15
7.3
3.45
2.5
2.5
5.0
T
8.6
4.9
6.9
5.7
7.1
9.0
10
1
50
Min
Typ
2.2
2.2
1.1
3.3
5.5
7.7
9.9
12.1
14.3
Max
5.0
5.0
1.4
3.6
5.8
8.0
10.2
12.4
14.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
µs
RxCLK IN to RxCLK OUT Delay 25˚C, V
CC
= 3.3V
(Figure 10 )
Note 5:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter-
ference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
DS012886-2
FIGURE 1. “Worst Case” Test Pattern
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