Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
Parameter
LVDS Low-to-High Transition Time
(Figure 3 )
LVDS High-to-Low Transition Time
(Figure 3 )
TxCLK IN Transition Time
(Figure 5 )
TxOUT Channel-to-Channel Skew
(Figure 6 )
Transmitter Output Pulse Position for Bit 0
(Figure 17 )
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period
(Figure 7)
TxCLK IN High Time
(Figure 7)
TxCLK IN Low Time
(Figure 7)
TxIN Setup to TxCLK IN
(Figure 7 )
TxIN Hold to TxCLK IN
(Figure 7 )
TxCLK IN to TxCLK OUT Delay 25˚C, V
CC
= 3.3V
(Figure 9 )
Transmitter Phase Lock Loop Set
(Figure 11 )
Transmitter Power Down Delay
(Figure 15 )
f = 65 MHz
f = 65 MHz
−0.4
1.8
4.0
6.2
8.4
10.6
12.8
15
0.35T
0.35T
2.5
0
3.0
3.7
5.5
10
100
250
0
2.2
4.4
6.6
8.8
11.0
13.2
T
0.5T
0.5T
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
Min
Typ
0.75
0.75
Max
1.5
1.5
5
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
5
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