22.0 Instruction Set (Continued)
← ← ←
[SP] PL, [SP−1] PU,SP−2, PC ii
JSRL
JSR
Addr.
Addr.
Addr
Jump SubRoutine Long
Jump SubRoutine
←
←
←
[SP] PL, [SP−1] PU,SP−2, PC9…0 i
← ←
[SP] PL, [SP−1] PU,SP−2,
JSRB
Jump SubRoutine Boot ROM
←
←
PL Addr,PU 00, switch to flash
←
PL ROM (PU,A)
JID
Jump InDirect
← ←
SP + 2, PL [SP], PU [SP−1]
RET
RETurn from subroutine
RETurn and SKip
←
←
RETSK
SP + 2, PL [SP],PU [SP−1],
skip next instruction
←
←
←
RETI
INTR
NOP
RETurn from Interrupt
Generate an Interrupt
No OPeration
SP + 2, PL [SP],PU [SP−1],GIE 1
←
←
←
[SP] PL, [SP−1] PU, SP−2, PC 0FF
←
PC PC + 1
22.7 INSTRUCTION EXECUTION TIME
Instructions Using A & C
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
CLRA
INCA
DECA
LAID
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
DCORA
RRCA
RLCA
SWAPA
SC
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
RC
Arithmetic and Logic Instructions
IFC
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
Immed.
2/2
IFNC
ADD
ADC
SUBC
AND
OR
PUSHA
POPA
ANDSZ
3/4
2/2
3/4
2/2
3/4
2/2
Transfer of Control Instructions
3/4
2/2
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
3/4
2/2
JMPL
JMP
JP
3/4
2/3
1/3
3/5
2/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
3/4
2/2
3/4
2/2
JSRL
JSR
1/3
3/4
3/4
3/4
1/1
1/1
1/1
JSRB
JID
VIS
RET
RETSK
RETI
INTR
NOP
RPND
1/1
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