22.0 Instruction Set (Continued)
22.6 INSTRUCTION SET SUMMARY
←
←
ADD
ADC
A,Meml
A,Meml
ADD
A
A
A + Meml
A + Meml + C, C Carry,
←
ADD with Carry
←
HC Half Carry
← ←
A − MemI + C, C Carry,
SUBC
A,Meml
Subtract with Carry
A
←
HC Half Carry
←
AND
A,Meml
Logical AND
A
A and Meml
Skip next if (A and Imm) = 0
ANDSZ A,Imm
Logical AND Immed., Skip if Zero
Logical OR
←
←
OR
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
A
A
A or Meml
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
X
Logical EXclusive OR
IF EQual
A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
IF EQual
≠
Compare A and Meml, Do next if A Meml
>
Compare A and Meml, Do next if A Meml
≠
Do next if lower 4 bits of B Imm
IF Not Equal
IF Greater Than
If B Not Equal
←
Reg
Decrement Reg., Skip if Zero
Set BIT
Reg Reg − 1, Skip if Reg = 0
#,Mem
#,Mem
#,Mem
1 to bit, Mem (bit = 0 to 7 immediate)
0 to bit, Mem
Reset BIT
IF BIT
If bit #,A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
CLeaR A
↔
↔
←
←
←
A,Mem
A,[X]
A
A
A
A
B
Mem
[X]
X
LD
A,Meml
A,[X]
Meml
[X]
LD
LD
B,Imm
Mem,Imm
Reg,Imm
A, [B ]
A, [X ]
A, [B ]
A, [X ]
[B ],Imm
A
Imm
←
Mem Imm
LD
←
Reg Imm
↔
↔
←
←
LD
←
[B], (B B 1)
X
A
A
A
A
←
[X], (X X 1)
X
←
[B], (B B 1)
LD
←
[X], (X X 1)
LD
← ←
[B] Imm, (B B 1)
LD
←
A
←
A
←
A
←
A
←
A
→
C
←
C
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
0
A
INCrement A
A + 1
A
DECrement A
A − 1
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
ROM (PU,A)
A
A
A
A
BCD correction of A (follows ADC, SUBC)
→
←
→
←
→
A0 C
A7
A7
…
…
←
←
A0 C, HC A0
↔
A7…A4 A3…A0
←
←
←
←
C
C
1, HC
0, HC
1
0
RC
Reset C
IFC
IF C
IF C is true, do next instruction
IFNC
POP
PUSH
VIS
IF Not C
If C is not true, do next instruction
← ←
SP SP + 1, A [SP]
A
A
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
←
←
[SP] A, SP SP − 1
←
←
PU [VU], PL [VL]
←
PC ii (ii = 15 bits, 0 to 32k)
JMPL
JMP
JP
Addr.
Addr.
Disp.
←
PC9…0 i (i = 12 bits)
←
PC PC + r (r is −31 to +32, except 1)
Jump relative short
73
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