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COP8AME9EMW8 参数 Datasheet PDF下载

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型号: COP8AME9EMW8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS闪存微控制器,具有8K内存,双通道运算放大器,虚拟EEROM ,温度传感器, 10位A / D和掉电复位 [8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset]
分类和应用: 闪存传感器温度传感器微控制器和处理器外围集成电路运算放大器光电二极管时钟
文件页数/大小: 83 页 / 908 K
品牌: NSC [ National Semiconductor ]
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11.0 In-System Programming (Continued)  
TABLE 12. Register and Bit Name Definitions  
Register  
Name  
RAM  
Location  
0xA9  
Purpose  
ISPADHI  
High byte of Flash Memory Address  
Low byte of Flash Memory Address  
ISPADLO  
ISPWR  
0xA8  
The user must store the byte to be written into this register before jumping into the  
write byte routine.  
0xAB  
ISPRD  
Data will be returned to this register after the read byte routine execution.  
The ISPKEY Register is required to validate the JSRB instruction and must be loaded  
within 6 instruction cycles before the JSRB.  
0xAA  
0xE2  
ISPKEY  
BYTECOUNTLO  
PGMTIM  
Holds the count of the number of bytes to be read or written in block operations.  
Write Timing Register. This register must be loaded, by the user, with the proper value  
before execution of any USER ISP Write or Erase operation. Refer to Table 8 for the  
correct value.  
0xF1  
0xE1  
Confirmation Code  
KEY  
The user must place this code in the accumulator before execution of a Flash Memory  
Mass Erase command.  
A
Must be transferred to the ISPKEY register before execution of a JSRB instruction.  
0x98  
11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING  
ISP ROUTINES IN BOOT ROM  
the same location in Flash memory. Two writes to  
the same location without an intervening erase will  
produce unpredicatable results including possible  
disturbance of unassociated locations.  
1. The hardware will disable interrupts from occurring. The  
hardware will leave the GIE bit in its current state, and if  
set, the hardware interrupts will occur when execution is  
returned to Flash Memory. Subsequent interrupts, dur-  
ing ISP operation, from the same interrupt source will be  
lost. Interrupt may occur between setting the KEY  
and executing the JSRB instruction. In this case, the  
KEY will expire before the JSRB is executed. It is,  
therefore, recommended that the software globally  
disable interrupts before setting the Key.  
11.10 FLASH MEMORY DURABILITY CONSIDERATIONS  
The endurance of the Flash Memory (number of possible  
Erase/Write cycles) is a function of the erase time and the  
lowest temperature at which the erasure occurs. If the device  
is to be used at low temperature, additional erase operations  
can be used to extend the erase time. The user can deter-  
mine how many times to erase a page based on what  
endurance is desired for the application (e.g. four page  
erase cycles, each time a page erase is done, may be  
required to achieve the typical 100k Erase/Write cycles in an  
application which may be operating down to 0˚C). Also, the  
customer can verify that the entire page is erased, with  
software, and request additional erase operations if desired.  
2. The security feature in the MICROWIRE/PLUS ISP is  
guaranteed by software and not hardware. When ex-  
ecuting the MICROWIRE/PLUS ISP routine, the security  
bit is checked prior to performing all instructions. Only  
the mass erase command, write PGMTIM register, and  
reading the Option register is permitted within the  
MICROWIRE/PLUS ISP routine. When the user is per-  
forming his own ISP, all commands are permitted. The  
entry points from the user’s ISP code do not check for  
security. It is the burden of the user to guarantee his own  
security. See the Security bit description in Section 10.5  
OPTION REGISTER for more details on security.  
TABLE 13. Typical Flash Memory Endurance  
Low End of Operating Temp Range  
>
25˚C  
Erase  
Time  
1 ms  
2 ms  
3 ms  
4 ms  
5 ms  
6 ms  
7 ms  
8 ms  
−40˚C  
−20˚C  
0˚C  
25˚C  
3. When using any of the ISP functions in Boot ROM, the  
ISP routines will service the WATCHDOG within the  
selected upper window. Upon return to flash memory,  
the WATCHDOG is serviced, the lower window is en-  
abled, and the user can service the WATCHDOG any-  
time following exit from Boot ROM, but must service it  
within the selected upper window to avoid a WATCH-  
DOG error.  
60k  
60k  
60k  
60k  
70k  
80k  
90k  
100k  
60k  
60k  
60k  
60k  
70k  
80k  
90k  
100k  
60k  
60k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
100k  
60k  
100k  
100k  
100k  
100k  
100k  
4. Block Writes can start anywhere in the page of Flash  
memory, but cannot cross half page or full page bound-  
aries.  
5. The user must ensure that a page erase or a mass  
erase is executed between two consecutive writes to  
29  
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