AC Electrical Characteristics (Continued)
=
The following specifications apply for VCC 5 VDC and TMIN≤TA≤TMAX unless otherwise specified.
Symbol Parameter Conditions Min
COUT TRI-STATE Output
Capacitance (Data Buffers)
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
Typ
Max
Units
5
7.5
pF
=
VIN (1)
VIN (0)
IIN (1)
IIN (0)
Logical “1” Input Voltage
(Except Pin 4 CLK IN)
Logical “0” Input Voltage
(Except Pin 4 CLK IN)
Logical “1” Input Current
(All Inputs)
VCC 5.25 VDC
2.0
15
0.8
1
VDC
=
VCC 4.75 VDC
VDC
=
VIN 5 VDC
0.005
µADC
µADC
=
Logical “0” Input Current
(All Inputs)
VIN 0 VDC
−1
−0.005
CLOCK IN AND CLOCK R
VT+
CLK IN (Pin 4) Positive Going
2.7
1.5
0.6
3.1
1.8
1.3
3.5
2.1
2.0
0.4
VDC
VDC
VDC
VDC
VDC
Threshold Voltage
CLK IN (Pin 4) Negative
Going Threshold Voltage
CLK IN (Pin 4) Hysteresis
(VT+)−(VT−)
VT−
VH
=
IO 360 µA
VOUT (0)
VOUT (1)
Logical “0” CLK R Output
Voltage
=
VCC 4.75 VDC
=
Logical “1” CLK R Output
Voltage
IO −360 µA
2.4
=
VCC 4.75 VDC
DATA OUTPUTS AND INTR
VOUT (0)
Logical “0” Output Voltage
=
=
Data Outputs
IOUT 1.6 mA, VCC 4.75 VDC
0.4
0.4
VDC
VDC
= =
IOUT 1.0 mA, VCC 4.75 VDC
INTR Output
=
=
VOUT (1)
VOUT (1)
IOUT
Logical “1” Output Voltage
Logical “1” Output Voltage
TRI-STATE Disabled Output
Leakage (All Data Buffers)
IO −360 µA, VCC 4.75 VDC
2.4
4.5
−3
VDC
=
=
IO −10 µA, VCC 4.75 VDC
VDC
=
VOUT 0 VDC
µADC
µADC
mADC
mADC
=
VOUT 5 VDC
3
=
ISOURCE
ISINK
POWER SUPPLY
ICC Supply Current (Includes
VOUT Short to Gnd, TA 25˚C
4.5
9.0
6
=
VOUT Short to VCC, TA 25˚C
16
=
fCLK 640 kHz,
= =
VREF/2 NC, TA 25˚C
Ladder Current)
=
and CS 5V
ADC0801/02/03/04LCJ/05
ADC0804LCN/LCWM
1.1
1.9
1.8
2.5
mA
mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from V
CC
to Gnd and has a typical breakdown voltage of 7 V .
DC
Note 4: For V (−)≥ V (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct
IN IN
for analog input voltages one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V levels (4.5V), as high
CC
level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50 mV forward bias of either diode. This means that as long as the analog V does not exceed the supply voltage by more than 50 mV, the output code will be correct.
IN
To achieve an absolute 0 V to 5 V input voltage range will therefore require a minimum supply voltage of 4.950 V over temperature variations, initial tolerance
DC
DC
DC
and loading.
=
Note 5: Accuracy is guaranteed at f
640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex-
CLK
tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 4 and section 2.0.
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