Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Infrared (15 seconds)
220˚C
−65˚C to +150˚C
875 mW
Storage Temperature Range
=
Package Dissipation at TA 25˚C
ESD Susceptibility (Note 10)
800V
Supply Voltage (VCC) (Note 3)
Voltage
6.5V
Operating Ratings (Notes 1, 2)
Logic Control Inputs
−0.3V to +18V
Temperature Range
ADC0804LCJ
TMIN≤TA≤TMAX
At Other Input and Outputs
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
−0.3V to (VCC+0.3V)
−40˚C≤TA≤+85˚C
−40˚C≤TA≤+85˚C
0˚C≤TA≤+70˚C
0˚C≤TA≤+70˚C
ADC0801/02/03/05LCN
ADC0804LCN
260˚C
300˚C
ADC0802/04LCWM
Range of VCC
4.5 VDC to 6.3 VDC
215˚C
Electrical Characteristics
=
=
The following specifications apply for VCC 5 VDC, TMIN≤TA≤TMAX and fCLK 640 kHz unless otherwise specified.
Parameter
Conditions
With Full-Scale Adj.
(See Section 2.5.2)
=
Min
Typ
Max
Units
1
±
ADC0801: Total Adjusted Error (Note 8)
⁄4
LSB
1
1
±
±
ADC0802: Total Unadjusted Error (Note 8)
ADC0803: Total Adjusted Error (Note 8)
V
REF/2 2.500 VDC
⁄
2
2
LSB
LSB
With Full-Scale Adj.
(See Section 2.5.2)
=
⁄
±
ADC0804: Total Unadjusted Error (Note 8)
ADC0805: Total Unadjusted Error (Note 8)
V
V
REF/2 2.500 VDC
1
1
LSB
LSB
kΩ
±
REF/2-No Connection
V
REF/2 Input Resistance (Pin 9)
ADC0801/02/03/05
ADC0804 (Note 9)
(Note 4) V(+) or V(−)
Over Analog Input Voltage
Range
2.5
0.75
8.0
1.1
kΩ
Analog Input Voltage Range
DC Common-Mode Error
Gnd–0.05
V
CC+0.05
VDC
LSB
1
±
±
1/16
1/16
⁄8
1
=
±
±
±
Power Supply Sensitivity
VCC 5 VDC 10% Over
Allowed VIN(+) and VIN(−)
Voltage Range (Note 4)
⁄8
LSB
AC Electrical Characteristics
=
The following specifications apply for VCC 5 VDC and TMIN≤TA≤TMAX unless otherwise specified.
Symbol
TC
Parameter
Conversion Time
Conditions
Min
103
66
Typ
Max
114
73
Units
µs
=
fCLK 640 kHz (Note 6)
(Notes 5, 6)
TC
Conversion Time
1/fCLK
kHz
=
fCLK
Clock Frequency
VCC 5V, (Note 5)
100
40
640
1460
60
Clock Duty Cycle
%
CR
Conversion Rate in Free-Running
Mode
INTR tied to WR with
8770
9708
conv/s
=
=
CS 0 VDC, fCLK 640 kHz
=
tW(WR)L
tACC
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-Z State)
CS 0 VDC (Note 7)
100
ns
ns
=
CL 100 pF
135
125
200
200
=
=
t1H, t0H
CL 10 pF, RL 10k
(See TRI-STATE Test
Circuits)
ns
t
WI, tRI
Delay from Falling Edge
of WR or RD to Reset of INTR
Input Capacitance of Logic
Control Inputs
300
5
450
7.5
ns
CIN
pF
3
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