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30141-23 参数 Datasheet PDF下载

30141-23图片预览
型号: 30141-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用: 微控制器和处理器外围集成电路微处理器
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Power Management (Continued)  
indicate the start of packet transmission. The contents of  
the packet register are then shifted out starting from bit 7  
down to bit 0. PSERIAL is held high for one SYSCLK to  
indicate the end of packet transmission and then remains  
low until the next transmission interval. After the packet  
transmission has completed, the packet contents are  
cleared.  
6.6 GXM PROCESSOR SERIAL BUS  
The power management logic of the GXm processor pro-  
vides the CS5530 with information regarding the GXm  
processor productivity. If the GXm processor is deter-  
mined to be relatively inactive, the GXm processor power  
consumption can be greatly reduced by entering the Sus-  
pend Modulation mode.  
Although the majority of the system power management  
logic is implemented in the CS5530, a small amount of  
logic is required within the GXm processor to provide  
information from the graphics controller that is not exter-  
nally visible otherwise. The GXm processor implements a  
simple serial communications mechanism to transmit the  
CPU status to the CS5530. The GXm processor accumu-  
lates CPU events in a 8-bit register, “PM Serial Packet  
Register” (GX_BASE+850Ch, see Table 6-1), which is  
serially transmitted out of the GXm processor every 1 to  
6.7 POWER MANAGEMENT REGISTERS  
The GXm processor contains the power management  
registers for the serial packet transmission control, the  
user-defined power management address space, Sus-  
pend Refresh, and SMI status for Suspend/Resume.  
These registers are memory mapped (GX_BASE+8500h-  
8FFFh) in the address space of the GXm processor and  
are described in the following sections. Refer to Section  
4.1.2 “Control Registers” on page 94 for instructions on  
accessing these registers.  
µ
10 s. The transmission frequency is set with the “PM  
Serial Packet Control Register” (GX_BASE+8504h, see  
Table 6-1).  
Note, however, the PM_BASE and PM_MASK registers  
are accessed with the CPU_READ and CPU_WRITE  
instructions.  
Refer  
to  
Section  
4.1.6  
6.6.1 Serial Packet Transmission  
“CPU_READ/CPU_WRITE Instructions” on page 99 for  
more information regarding these instructions.  
The GXm processor transmits the contents of the “PM  
Serial Packet Register” on the SERIALP output pin to the  
PSERIAL input pin of the CS5530. The GXm processor  
holds SERIALP low until the transmission interval counter  
(GX_BASE+8504h[4:3]) has elapsed. Once the counter  
has elapsed, PSERIAL is held high for two SYSCLKs to  
Table 6-1 summarizes the above mentioned registers.  
Tables 6-2 and 6-3 starting on page 180 give these regis-  
ter’s bit formats.  
Table 6-1. Power Management Register Summary  
GX_BASE+  
Memory Offset  
Type  
Name/Function  
Default Value  
Control and Status Registers  
8500h-8503h  
8504h-8507h  
8508h-850Bh  
850Ch-850Fh  
R/W  
R/W  
R/W  
R/W  
PM_STAT_SMI  
xxxxxx00h  
PM SMI Status Register — Contains System Management Mode (SMM) status  
information used by SoftVGA.  
PM_CNTRL_TEN  
xxxxxx00h  
xxxxxx00h  
xxxxxx00h  
PM Serial Packet Control Register — Sets the serial packet transmission frequency  
and enables specific CPU events to be recorded in the serial packet.  
PM_CNTRL_CSTP  
PM Clock Stop Control Register — Enables the 3-V Suspend Mode for the GXm  
processor.  
PM_SER_PACK  
PM Serial Packet Register — Transmits the contents of the serial packet.  
Programmable Address Region Registers  
FFFF FF6Ch  
FFFF FF7Ch  
R/W  
R/W  
PM_BASE  
00000000h  
00000000h  
PM Base Register — Contains the base address for the programmable memory  
range decode. This register, in combination with the PM_MASK register, is used to  
generate a memory range decode which sets bit 1 in the serial transmission packet.  
PM_MASK  
PM Mask Register — The address mask for the PM_BASE register  
Revision 3.1  
179  
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