Instruction Set (Continued)
9.2 CPUID INSTRUCTION
The CPUID instruction (opcode 0FA2) allows the software
to make processor inquiries as to the vendor, family,
model, stepping, features and also provides cache infor-
mation. The GXm with MMX supports both the standard
and National Semiconductor extended CPUID levels.
Table 9-17. CPUID Data Returned when EAX = 0
Register
(Note)
Returned Contents
Description
EAX
2
Maximum Standard
Level
The presence of the CPUID instruction is indicated by the
ability to change the value of the ID Flag, bit 21 in the
EFLAGS register.
EBX
EDX
ECX
69
(iryC)
72
6E
61
7943
Vendor ID String 1
Vendor ID String 2
Vendor ID String 3
73
(snlx)
4978
6574
The CPUID level allows the CPUID instruction to return
different information in the EAX, EBX, ECX, and EDX reg-
isters. The level is determined by the initialized value of
the EAX register before the instruction is executed. A
summary of the CPUID levels is shown in Table 9-16.
64
(daet)
Note: The register column is intentionally out of order.
9.2.1.2 CPUID Instruction with EAX = 00000001h
Standard function 01h (EAX = 1) of the CPUID instruction
returns the processor type, family, model, and stepping
information of the current processor in the EAX register
(see Table 9-18). The EBX and ECX registers are
reserved.
Table 9-16. CPUID Levels Summary
Initialized
CPUID
Type
EAX
Register
Returned Data in EAX, EBX,
ECX, EDX Registers
Standard
00000000h Maximum standard levels, CPU
vendor string
Table 9-18. EAX, EBX, ECX CPUID Data
Returned when EAX = 1
Standard
Standard
Extended
Extended
00000001h Model, family, type and features
00000002h TLB and cache information
80000000h Maximum extended levels
Returned
Register
EAX[3:0]
Contents
Description
Stepping ID
80000001h Extended model, family, type and
features
xx
4
5
0
-
EAX[7:4]
EAX[11:8]
EAX[15:12]
EAX[31:16]
EBX
Model
Extended
Extended
Extended
Extended
80000002h CPU marketing name string
80000003h
Family
Type
80000004h
Reserved
Reserved
Reserved
80000005h TLB and L1 cache description
-
ECX
-
9.2.1 Standard CPUID Levels
The standard CPUID levels are part of the standard x86
instruction set.
The standard feature flags supported are returned in the
EDX register as shown in Table 9-19 on page 209. Each
flag refers to a specific feature and indicates if that feature
is present on the processor. Some of these features have
protection control in CR4. Before using any of these fea-
tures on the processor, the software should check the cor-
responding feature flag. Attempting to execute an
unavailable feature can cause exceptions and unexpected
behavior. For example, software must check bit 4 before
attempting to use the Time Stamp Counter instruction.
9.2.1.1 CPUID Instruction with EAX = 00000000h
Standard function 0h (EAX = 0) of the CPUID instruction
returns the maximum standard CPUID levels as well as
the processor vendor string.
After the instruction is executed, the EAX register contains
the maximum standard CPUID levels supported. The
maximum standard CPUID level is the highest acceptable
value for the EAX register input. This does not include the
extended CPUID levels.
The EBX through EDX registers contain the vendor string
of the processor as shown in Table 9-17.
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