Instruction Set (Continued)
9.3 PROCESSOR CORE INSTRUCTION SET
The instruction set for the GXm processor core is summa-
rized in Table 9-27 on page 213. The table uses several
symbols and abbreviations that are described next and
listed in Table 9-26.
Table 9-26. Processor Core Instruction Set
Table Legend
Symbol or
Abbreviation
Description
Opcode
Opcodes
#
##
Immediate 8-bit data
Opcodes are given as hex values except when they
appear within brackets as binary values.
Immediate 16-bit data
###
+
Full immediate 32-bit data (8, 16, 32 bits)
8-bit signed displacement
Clock Counts
+++
Full signed displacement (16, 32 bits)
The clock counts listed in the instruction set summary
table are grouped by operating mode (Real and Pro-
tected) and whether there is a register/cache hit or a
cache miss. In some cases, more than one clock count is
shown in a column for a given instruction, or a variable is
used in the clock count.
Clock Count
/
n
L
|
Register operand/memory operand.
Number of times operation is repeated.
Level of the stack frame.
Conditional jump taken | Conditional jump not
taken.
Flags
(e.g. “4|1” = 4 clocks if jump taken, 1 clock if
jump not taken)
There are nine flags that are affected by the execution of
instructions. The flag names have been abbreviated and vari-
ous conventions used to indicate what effect the instruc-
tion has on the particular flag.
\
CPL ≤ IOPL \ CPL > IOPL
(where CPL = Current Privilege Level, IOPL =
I/O Privilege Level)
Flags
OF
DF
IF
Overflow Flag
Direction Flag
Interrupt Enable Flag
Trap Flag
TF
SF
ZF
AF
PF
CF
x
Sign Flag
Zero Flag
Auxiliary Flag
Parity Flag
Carry Flag
Flag is modified by the instruction.
Flag is not changed by the instruction.
Flag is reset to “0”.
Flag is set to “1”.
-
0
1
u
Flag is undefined following execution the
instruction.
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