Signal Definitions (Continued)
2.2.5 Power, Ground, and No Connect Signals
BGA
SPGA
Signal Name
Pin No.
Pin No.
Type
Description
VSS
Refer
to
Refer
to
GND
Ground Connection
Table 2-3 Table 2-5
(Total of
71)
(Total of
50)
VCC2
VCC3
NC
Refer
to
Table 2-3 Table 2-5
(Total of
32)
Refer
to
PWR
PWR
2.2V, 2.5V, or 2.9V (Nominal) Core Power Connection
3.3V (Nominal) I/O Power Connection
(Total of
32)
Refer
to
Table 2-3 Table 2-5
(Total of
32)
Refer
to
(Total of
18)
D26,
E24,
AC5
E37,
F36, Q5,
X2, Z2,
AM36
No Connection
A line designated as NC must be left disconnected.
2.2.6 Internal Test and Measurement Signals
BGA SPGA
Signal Name
Pin No. Pin No.
Type
Description
Float
FLT#
AC2
AJ3
I
Float forces the GXLV processor to float all outputs in the high-
impedance state and to enter a power-down state.
RW_CLK
TEST[3:0]
AE6
AL11
O
O
Raw Clock
This output is the GXLV processor clock. This debug signal can
be used to verify clock operation.
B22,
A23,
B21,
C21
D28,
B32,
D26,
A33
SDRAM Test Outputs
These outputs are used for internal debug only.
TCLK
TDI
J2
(PU)
P4
(PU)
I
I
Test Clock
JTAG test clock.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
D2
F4
Test Data Input
(PU)
(PU)
JTAG serial test-data input.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
TDO
F1
J1
O
Test Data Output
JTAG serial test-data output.
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