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30134-23 参数 Datasheet PDF下载

30134-23图片预览
型号: 30134-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用: 外围集成电路时钟
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Signal Definitions (Continued)  
2.2.4 Video Interface Signals (Continued)  
BGA  
SPGA  
Signal Name  
Pin No  
Pin No  
Type  
Description  
FP_HSYNC  
L2  
R4  
O
Flat Panel Horizontal Sync  
Flat Panel Horizontal Sync establishes the line rate and horizon-  
tal retrace interval for a TFT display. Polarity is programmable.  
(See Table 4-31 on page 146 for programming information.)  
This signal is an input to the CS5530. The CS5530 re-drives this  
signal to the flat panel.  
If no flat panel is used in the system, this signal is not connected.  
FP_VSYNC  
J1  
P2  
O
Flat Panel Vertical Sync  
Flat Panel Vertical Sync establishes the screen refresh rate and  
vertical retrace interval for a TFT display. Polarity is programma-  
ble. (See Table 4-31 on page 146 for programming information.)  
This signal is an input to the CS5530. The CS5530 re-drives this  
signal to the flat panel.  
If no flat panel is used in the system, this signal is not connected.  
ENA_DISP  
VID_RDY  
AD5  
AM6  
O
Display Enable  
Display Enable indicates the active display portion of a scan line  
to the CS5530.  
In a CS5530-based system, this signal is required to be con-  
nected.  
AD1  
M2  
AK2  
S3  
I
Video Ready  
This input signal indicates that the video FIFO in the CS5530 is  
ready to receive more data.  
VID_VAL  
O
O
Video Valid  
VID_VAL indicates that video data to the CS5530 is valid.  
VID_DATA[7:0]  
Refer  
to  
Table 2-3 Table 2-5  
Refer  
to  
Video Data Bus  
When the Video Port is enabled, this bus drives Video (YUV or  
RGB 5:6:5) data synchronous to the VID_CLK output.  
PIXEL[17:0]  
Refer  
to  
Table 2-3 Table 2-5  
Refer  
to  
O
Graphics Pixel Data Bus  
This bus drives graphics pixel data synchronous to the PCLK  
output.  
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