Signal Definitions (Continued)
2.2.3 Memory Controller Interface Signals (Continued)
BGA
SPGA
Signal Name
Pin No.
Pin No.
Type
Description
DQM[7:0]
Refer
to
Table 2-3 Table 2-5
Refer
to
O
Data Mask Control Bits
During memory read cycles, these outputs control whether the
SDRAM output buffers are driven on the MD bus or not. All DQM
signals are asserted during read cycles.
During memory write cycles, these outputs control whether or
not MD data will be written into the SDRAM.
DQM[0] is associated with MD[7:0].
DQM[7] is associated with MD[63:56].
SDCLK[3:0]
AE4,
AF5,
AE5,
AF4
AM8,
AK10,
AL7,
O
SDRAM Clocks
The SDRAM devices sample all the control, address, and data
based on these clocks.
AK8
SDCLK_IN
AE8
AK12
I
SDRAM Clock Input
The GXLV processor samples the memory read data on this
clock. Works in conjunction with the SDCLK_OUT signal.
SDCLK_OUT
AF8
AL13
O
SDRAM Clock Output
This output is routed back to SDCLK_IN. The board designer
should vary the length of the board trace to control skew
between SDCLK_IN and SDCLK.
2.2.4 Video Interface Signals
BGA
SPGA
Signal Name
Pin No
Pin No
Type
Description
PCLK
AC1
AJ1
O
Pixel Port Clock
PCLK is the pixel dot clock output. It clocks the pixel data from
the GXLV processor to the CS5530.
VID_CLK
DCLK
P1
V4
O
I
Video Clock
VID_CLK is the video port clock to the CS5530.
AB1
AD4
Dot Clock
The DCLK input is driven from the CS5530 and is the pixel dot
clock. In some cases this clock can be a 2x multiple of PCLK
CRT_HSYNC
CRT_VSYNC
W2
AD2
AH2
O
O
CRT Horizontal Sync
CRT Horizontal Sync establishes the line rate and horizontal
retrace interval for an attached CRT. The polarity is programma-
ble. See DC-Timing_CFG Register in Table 4-29 on page 146 for
programming information.
AA3
CRT Vertical Sync
CRT Vertical Sync establishes the screen refresh rate and verti-
cal retrace interval for an attached CRT. The polarity is program-
mable. See DC-Timing_CFG Register in Table 4-29 on page 147
for programming information.
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