Processor Programming (Continued)
3.11.6 SMM Instructions
If any one of the conditions above is not met and an
attempt is made to execute an SVDC, RSDC, SVLDT,
RSLDT, SVTS, RSTS, or RSM instruction, an invalid
opcode exception is generated. The SMM instructions can
be executed outside of defined SMM space provided the
conditions above are met.
The GXm processor core automatically saves the minimal
amount of CPU state information when entering an SMM
cycle that allows fast SMM service-routine entry and exit.
After entering the SMM service routine, the MOV, SVDC,
SVLDT and SVTS instructions can be used to save the
complete CPU state information. If the SMM service rou-
tine modifies more state information than is automatically
saved or if it forces the CPU to power down, the complete
CPU state information must be saved. Since the CPU is a
static device, its internal state is retained when the input
clock is stopped. Therefore, an entire CPU-state save is
not necessary before stopping the input clock.
The SMINT instruction can be used by software to enter
SMM. The SMINT instruction can only be used outside an
SMM routine if all the conditions listed below are true.
1) USE_SMI = 1
2) SMAR size > 0
3) Current Privilege Level = 0
4) SMAC = 1
The SMM instructions, listed in Table 3-37, can be exe-
cuted only if all the conditions listed below are met.
1) USE_SMI = 1.
If SMI# is asserted to the CPU during a software SMI, the
hardware SMI# is serviced after the software SMI has
been exited by execution of the RSM instruction.
2) SMAR SIZE > 0.
3) Current Privilege level = 0.
All the SMM instructions (except RSM and SMINT) save
or restore 80 bits of data, allowing the saved values to
include the hidden portion of the register contents.
4) SMAC bit is high or the CPU is in an SMI service
routine.
Table 3-37. SMM Instruction Set
Instruction
Opcode
Format
Description
SVDC
0F 78h [mod sreg3 r/m]
SVDC mem80, sreg3
Save Segment Register and Descriptor
Saves reg (DS, ES, FS, GS, or SS) to mem80.
Restore Segment Register and Descriptor
RSDC
0F 79h [mod sreg3 r/m]
RSDC sreg3, mem80
Restores reg (DS, ES, FS, GS, or SS) from mem80. Use RSM
to restore CS.
Note: Processing “RSDC CS, Mem80” will produce an excep-
tion.
SVLDT
RSLDT
SVTS
0F 7Ah [mod 000 r/m]
0F 7Bh [mod 000 r/m]
0F 7Ch [mod 000 r/m]
0F 7Dh [mod 000 r/m]
0F 38h
SVLDT mem80
RSLDT mem80
SVTS mem80
RSTS mem80
SMINT
Save LDTR and Descriptor
Saves Local Descriptor Table (LDTR) to mem80.
Restore LDTR and Descriptor
Restores Local Descriptor Table (LDTR) from mem80.
Save TSR and Descriptor
Saves Task State Register (TSR) to mem80.
Restore TSR and Descriptor
RSTS
Restores Task State Register (TSR) from mem80.
Software SMM Entry
SMINT
CPU enters SMM. CPU state information is saved in SMM
memory space header and execution begins at SMM base
address.
RSM
0F AAh
RSM
Resume Normal Mode
Exits SMM. The CPU state is restored using the SMM memory
space header and execution resumes at interrupted point.
Note: smem80 = 80-bit memory location.
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