Processor Programming (Continued)
Table 3-36. SMM Memory Space Header Description
Name
Description
Size
DR7
Debug Register 7: The contents of Debug Register 7.
4 Bytes
4 Bytes
4 Bytes
4 Bytes
EFLAGS
CR0
Extended FLAGS Register: The contents of Extended FLAGS Register.
Control Register 0: The contents of Control Register 0.
Current IP
Current Instruction Pointer: The address of the instruction executed prior to servicing SMM
interrupt.
Next IP
Next Instruction Pointer: The address of the next instruction that will be executed after exiting
4 Bytes
SMM.
CS Selector
Code Segment Selector: Code segment register selector for the current code segment.
Code Segment Descriptor: Encoded descriptor bits for the current code segment.
Nested SMI Status: Flag that determines whether an SMI occurred during SMM (i.e., nested)
SoftVGA SMI Status: SMI was generated by an access to VGA region.
External SMI Status:
2 Bytes
8 Bytes
1 Bit
CS Descriptor
N
V
X
1 Bit
1 Bit
If = 1: SMI generated by external SMI# pin
If = 0: SMI internally generated by Internal Bus Interface Unit.
M
H
Memory or I/O Access: 0 = I/O access; 1 = Memory access.
1 Bit
1 Bit
Halt Status: Indicates that the processor was in a halt or shutdown prior to servicing the SMM
interrupt.
S
Software SMM Entry Indicator:
1 Bit
1 Bit
If = 1: Current SMM is the result of an SMINT instruction.
If = 0: Current SMM is not the result of an SMINT instruction.
P
REP INSx/OUTSx Indicator:
If = 1: Current instruction has a REP prefix.
If = 0: Current instruction does not have a REP prefix.
I
IN, INSx, OUT, or OUTSx Indicator:
1 Bit
If = 1: Current instruction performed is an I/O WRITE.
If = 0: Current instruction performed is an I/O READ.
C
CS Writable: Code Segment Writable
1 Bit
If = 1: CS is writable
If = 0: CS is not writable
I/O Data Size
Indicates size of data for the trapped I/O cycle:
2 Bytes
01h = byte
03h = word
0Fh = DWORD
I/O Address
Processor port used for the trapped I/O cycle.
2 Bytes
4 Bytes
4 Bytes
I/O or Memory Data
Restored ESI or EDI
Data associated with the trapped I/O or memory cycleS.
Restored ESI or EDI Value: Used when it is necessary to repeat a REP OUTSx or REP INSx
instruction when one of the I/O cycles caused an SMI# trap.
Memory Address
Physical address of the operation that caused the SMI.
4 Bytes
Note: INSx = INS, INSB, INSW or INSD instruction.
OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction.
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