Processor Programming (Continued)
3.11.9.2 CPU States Related to SMM and Suspend
Mode
latched. (In order for INTR to be latched, the IF flag,
EFLAGS register bit 9, must be set.) The INTR or NMI is
serviced after exiting Suspend mode.
The state diagram shown in Figure 3-12 illustrates the var-
ious CPU states associated with SMM and Suspend
mode. While in the SMI service routine, the GXm proces-
sor core can enter Suspend mode either by (1) executing
a halt (HLT) instruction or (2) by asserting the SUSP#
input.
If Suspend mode is entered through a HLT instruction
from the operating system or application software, the
reception of an SMI# interrupt causes the CPU to exit
Suspend mode and enter SMM. If Suspend mode is
entered through the hardware (SUSP# = 0) while the
operating system or application software is active, the
CPU latches one occurrence of INTR, NMI, and SMI#.
During SMM operations and while in SUSP#-initiated
Suspend mode, an occurrence of either NMI or INTR is
Suspend Mode
(SUSPA# = 0)
NMI or INTR
Interrupt Service
Routine
IRET*
HLT*
NMI or INTR
SUSP# = 0
Suspend Mode
(SUSPA# = 0)
OS/Application
Software
RESET
SUSP# = 1
(INTR, NMI and SMI# latched)
SMI# = 0
SMINT*
SMI# = 0
RSM*
Non-SMM Operations
SMM Operations
SMI Service Routine
(SMI# = 0)
HLT*
Suspend Mode
(SUSPA# = 0)
IRET*
NMI or INTR
IRET*
SUSP# = 1
SUSP# = 0
NMI or INTR
Interrupt Service
Routine
Suspend Mode
(SUSPA# = 0)
Interrupt Service
Routine
*Instructions
(INTR and NMI latched)
Figure 3-12. SMM and Suspend Mode State Diagram
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