Processor Programming (Continued)
3.11.3 The SMI# Pin
3.11.5 SMM Memory Space Header
External chipsets can generate an SMI based on numer-
ous asynchronous events, including power management
timers, I/O address trapping, external devices, audio FIFO
events, and others. Since SMI# is edge sensitive, the
chipset must generate an edge for each of the events
above, requiring arbitration and storage of multiple SMM
events. These functions are provided by the CS5530 I/O
companion device. The processor generates an SMI
when the external pin changes from high-to-low or when
an RSM occurs if SMI# has not remained low since the
initiation of the previous SMI.
Tables 3-35 and show the SMM header. A memory
address field has been added to the end (offset –40h) of
the header for the GXm processor. Memory data will be
stored overlapping the I/O data, since these events can-
not occur simultaneously. The I/O address is valid for both
IN and OUT instructions, and I/O data is valid only for
OUT. The memory address is valid for read and write
operations, and memory data is valid only for write opera-
tions.
With every SMI interrupt or SMINT instruction, selected
CPU state information is automatically saved in the SMM
memory space header located at the top of SMM address
space. The header contains CPU state information that is
modified when servicing an SMM interrupt. Included in
this information are two pointers. The current IP points to
the instruction executing when the SMI was detected, but
it is valid only for an internal I/O SMI.
3.11.4 SMM Configuration Registers
The SMAR register specifies the base location of SMM
code region and its size limit. This SMAR register is identi-
cal to many of the National Semconductor processors.
A new configuration control register called SMHR has
been added to specify the 32-bit physical address of the
SMM header. The SMHR address must be 32-bit aligned
as the bottom two bits are ignored by the microcode.
Hardware will detect write operations to SMHR, and sig-
nal the microcode to recompute the header address.
Access to these registers is enabled by MAPEN (Index
C3h[4]).
The Next IP points to the instruction that will be executed
after exiting SMM. The contents of Debug Register 7
(DR7), the Extended FLAGS Register (EFLAGS), and
Control Register 0 (CR0) are also saved. If SMM has
been entered due to an I/O trap for a REP INSx or REP
OUTSx instruction, the Current IP and Next IP fields con-
tain the same addresses. In addition, the I and P fields con-
tain valid information.
The SMAR register writes to the SMM header when the
SMAR register is changed. For this reason, changes to
the SMAR register should be completed prior to setting up
the SMM header. The configuration registers bit formats
are detailed in Table 3-11 on page 49.
If entry into SMM is the result of an I/O trap, it is useful for
the programmer to know the port address, data size and
data value associated with that I/O operation. This informa-
tion is also saved in the header and is valid only if SMI# is
asserted during an I/O bus cycle. The I/O trap information is
not restored within the CPU when executing a RSM instruction.
Table 3-35. SMM Memory Space Header
Mem.
Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
-4h
DR7
EFLAGS
CR0
–8h
–Ch
–10h
–14h
–18h
–1Ch
–20h
–24h
–28h
–2Ch
–30h
–32h
Current IP
Next IP
RSVD
CS Selector
CS Descriptor [63:32]
CS Descriptor [31:0]
RSVD
RSVD
N
V
X
M
H
S
P
I
C
I/O Data Size
I/O Address [15:0]
I/O or Memory Data [31:0] (Note)
Restored ESI or EDI
Memory Address [31:0]
Note: Check the M bit at offset 24h to determine if the data is memory or I/O.
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