Virtual Subsystem Architecture (Continued)
control bit determines whether or not an SMI interrupt is
generated for the corresponding region. The purpose of
this hardware is to allow the VGA emulation software to
disable SMI interrupts in VGA memory regions that are
not currently displayed.
3DFh. The BC_XMAP_1 register (GX_BASE+8004h) in
the Internal Bus Interface Unit has an enable/disable bit
for each of the address ranges above.
5.2.3.3 VGA Configuration Registers
Table 5-2 summarizes the VGA Configuration Registers.
Detailed register/bit formats are given in Table 5-3.
For direct display modes (8 BPP or 16 BPP) in the display
controller, Virtual VGA can operate without SMI genera-
tion.
5.2.3.4 VGA Control Register
The VGA control register (VGACTL) provides control for
SMI generation through an enable bit for memory address
ranges A0000h to BFFFFh. Each bit controls whether or
not SMI is generated for accesses to the corresponding
address range. The default value of this register is zero so
that VGA accesses will not be trapped on systems with an
external VGA card.
The SMI generation circuit on the GXm processor has
configuration registers to control and mask SMI interrupts
in the VGA memory space.
5.2.3.2 VGA Memory Addresses
SMI generation can be configured to trap VGA memory
accesses in one of the following ranges:
A0000h to AFFFFh (EGA,VGA),
B0000h to B7FFFh (MDA),
or B8000h to BFFFFh (CGA).
5.2.3.5 VGA Mask Registers
The VGA Mask register (VGAM) has 32 bits that can
selectively mask 2 KB regions within the VGA memory
region A0000h to AFFFFh. If none of the three regions is
enabled in VGACTL, then the contents of VGAM are
ignored. VGAM can be used to prevent the occurrence of
SMI when non-displayed VGA memory is accessed. This
is an enhancement that improves performance for double-
buffered applications only.
Range selection is accomplished through programmable
bits in the VGACTL register (Index B9h). Fine control can
be exercised within the range selected to allow off-screen
accesses to occur without generating SMIs.
SMI generation can also separately control the following
I/O ranges: 3B0h to 3BFh, 3C0h to 3CFh, and 3D0h to
Table 5-2. VGA Configuration Registers Summary
Name Description
VGACTL VGA Control Register
VGAM VGA Mask Register
Index
Default
B9h
00h (SMI generation disabled)
Don’t Care
BAh-BDh
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