Virtual Subsystem Architecture (Continued)
5.2.3.6 VGA Range Detection
5.2.3.9 VGA Address Generator
The VGA range detection circuit is similar to the SMI gen-
eration hardware, however, it resides in the bus controller
address mapping unit. The purpose of this hardware is to
notify the graphics pipeline when accesses to the VGA
memory range A0000h to BFFFFh are detected. The
graphics pipeline has VGA read and write path hardware
to process VGA memory accesses. The VGA range
detection can be configured to trap VGA memory
accesses in one or more of the following ranges: A0000h
to AFFFFh (EGA,VGA), B0000h to B7FFFh (MDA), or
B8000h to BFFFFh (CGA).
The VGA address generator translates VGA memory
addresses up to address where the VGA memory resides
on the GXm processor. The VGA address generator
requires the address from the VGA access (A0000h to
BFFFFh), the base of the VGA memory on the GXm pro-
cessor, and various control bits. The control bits are nec-
essary because addressing is complicated by odd/even
and Chain 4 addressing modes.
5.2.3.10 VGA Memory
The VGA memory requires 256 KB of memory organized
as 64 KB by 32 bits. The VGA memory is implemented as
part of system memory. The GXm processor partitions
system memory into two areas, normal system memory
and graphics memory. System memory is mapped to the
normal physical address of the DRAM, starting at zero
and ending at memory size. Graphics memory is mapped
into high physical memory, contiguous to the registers and
dedicated cache of the GXm processor. The graphics
memory includes the frame buffer, compression buffer,
cursor memory, and VGA memory. The VGA memory is
mapped on a 256 KB boundary to simplify the address
generation.
5.2.3.7 VGA Sequencer
The VGA sequencer is located at the front end of the
graphics pipeline. The purpose of the VGA sequencer is
to divide up multiple-byte read and write operations into a
sequence of single-byte read and write operations. 16-bit
or 32-bit X-bus write operations to VGA memory are
divided into 8-bit write operations and sent to the VGA
write path. 16-bit or 32-bit X-bus read operations from
VGA memory are accumulated from 8-bit read operations
over the VGA read path. The sequencer generates the
lower two bits of the address.
5.2.3.8 VGA Write/Read Path
5.2.4 VGA Video BIOS
The VGA write path implements standard VGA write oper-
ations into VGA memory. No SMI is generated for write
path operations when the VGA access is not displayed.
When the VGA access is displayed, an SMI is generated
so that the SMI emulation can update the frame buffer.
The VGA write path converts 8-bit write operations from
the sequencer into 32-bit VGA memory write operations.
The operations performed by the VGA write path include
data rotation, raster operation (ALU), bit masking, plane
select, plane enable, and write modes.
The video BIOS supports the VESA BIOS Extensions
(VBE) Version 1.2 and 2.0, as well as all standard VGA
BIOS calls. It interacts with Virtual VGA through the use of
several extended VGA registers. These are virtual regis-
ters contained in the VSA code for Virtual VGA. (These
registers are defined in a separate document.)
The VGA read path implements standard VGA read oper-
ations from VGA memory. No SMI is needed for read-path
operations. The VGA read path converts 32-bit read oper-
ations from VGA memory to 8-bit data back to the
sequencer. The basic operations performed by the VGA
read path include color compare, plane-read select, and
read modes.
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