Processor Programming (Continued)
3.6.5 Exceptions in Real Mode
3.6.6 Error Codes
Many of the exceptions described in Table 3-29 "Interrupt
Vector Assignments" on page 80 are not applicable in real
mode. Exceptions 10, 11, and 14 do not occur in real
mode. Other exceptions have slightly different meanings
in real mode as listed in Table 3-31.
When operating in protected mode, the following exceptions
generate a 16-bit error code:
•
•
•
•
•
•
•
Double Fault
Alignment Check
Invalid TSS
Segment Not Present
Stack Fault
General Protection Fault
Page Fault
Table 3-31. Exception Changes in Real Mode
Vector
Number
Protected Mode
Function
Real Mode
Function
The error code format and bit definitions are shown in
Table 3-32. Bits [15:3] (selector index) are not meaningful
if the error code was generated as the result of a page
fault. The error code is always zero for double faults and
alignment check exceptions.
8
Double fault.
Invalid TSS.
Interrupt table limit overrun.
Does not occur.
10
11
Segment not
present.
Does not occur.
12
13
Stack fault.
SS segment limit overrun.
General protection CS, DS, ES, FS, GS seg-
fault.
ment limit overrun. In pro-
tected mode, an error code is
pushed. In real mode, no
error code is pushed.
14
Page fault.
Does not occur.
Table 3-32. Error Codes
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Selector Index
S2
S1
S0
Table 3-33. Error Code Bit Definitions
Fault
Type
Selector Index
(Bits 15:3)
S2 (Bit 2)
S1 (Bit 1)
S0 (Bit 0)
Page
Fault
Reserved.
Fault caused by:
Fault occurred during:
Fault occurred during
0 = Not present page
1 = Page-level protection
violation
0 = Read access
1 = Write access
0 = Supervisor access
1 = User access.
IDT Fault Index of faulty IDT Reserved
selector.
1
0
If = 1, exception occurred while
trying to invoke exception or
hardware interrupt handler.
Segment Index of faulty
Fault selector.
TI bit of faulty selector
If =1, exception occurred while
trying to invoke exception or
hardware interrupt handler.
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