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30036-23 参数 Datasheet PDF下载

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型号: 30036-23
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内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.6.4 Interrupt and Exception Priorities  
generated upon each attempt to execute the instruction.  
Each exception service routine should make the appropri-  
ate corrections to the instruction and then restart the  
instruction. In this way, exceptions can be serviced until  
the instruction executes properly.  
As the CPU executes instructions, it follows a consistent  
policy for prioritizing exceptions and hardware interrupts.  
The priorities for competing interrupts and exceptions are  
listed in Table 3-30. SMM interrupts always take prece-  
dence. Debug traps for the previous instruction and next  
instructions are handled as the next priority. When NMI  
and maskable INTR interrupts are both detected at the  
same instruction boundary, the GXLV processor services  
the NMI interrupt first.  
The CPU supports instruction restart after all faults,  
except when an instruction causes a task switch to a task  
whose Task State Segment (TSS) is partially not present.  
A TSS can be partially not present if the TSS is not page  
aligned and one of the pages where the TSS resides is  
not currently in memory.  
The CPU checks for exceptions in parallel with instruction  
decoding and execution. Several exceptions can result  
from a single instruction. However, only one exception is  
Table 3-30. Interrupt and Exception Priorities  
Priority  
Description  
Notes  
0
1
Reset.  
Caused by the assertion of RESET.  
SMM hardware interrupt.  
SMM interrupts are caused by SMI# asserted and always have  
highest priority.  
2
3
Debug traps and faults from previous instruction.  
Debug traps for next instruction.  
Includes single-step trap and data breakpoints specified in the  
debug registers.  
Includes instruction execution breakpoints specified in the debug  
registers.  
4
5
6
Non-maskable hardware interrupt.  
Maskable hardware interrupt.  
Caused by NMI asserted.  
Caused by INTR asserted and IF = 1.  
Faults resulting from fetching the next instruction.  
Includes segment not present, general protection fault and page  
fault.  
7
8
Faults resulting from instruction decoding.  
WAIT instruction and TS = 1 and MP = 1.  
ESC instruction and EM = 1 or TS = 1.  
Floating point error exception.  
Includes illegal opcode, instruction too long, or privilege violation.  
Device not available exception generated.  
9
Device not available exception generated.  
10  
11  
Caused by unmasked floating point exception with NE = 1.  
Includes segment not present, stack fault, and general protection  
Segmentation faults (for each memory reference  
required by the instruction) that prevent transferring fault.  
the entire memory operand.  
12  
13  
Page Faults that prevent transferring the entire  
memory operand.  
Alignment check fault.  
Revision 1.1  
81  
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