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30036-23 参数 Datasheet PDF下载

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型号: 30036-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
Single-step operation is enabled by setting the TF bit (bit  
8) in the EFLAGS register. When the TF is set, the CPU  
generates a debug exception (vector 1) after the execution  
of every instruction. Data breakpoints also generate a  
debug exception and are specified by loading the debug  
registers (DR0-DR3, see Table 3-12 on page 55) with the  
appropriate values.  
3.6.3.2 Interrupt Descriptor Table  
The interrupt vector number is used by the CPU to locate  
an entry in the interrupt descriptor table (IDT). In real  
mode, each IDT entry consists of a 4-byte far pointer to  
the beginning of the corresponding interrupt service rou-  
tine. In protected mode, each IDT entry is an 8-byte  
descriptor. The Interrupt Descriptor Table Register (IDTR)  
specifies the beginning address and limit of the IDT. Fol-  
lowing RESET, the IDTR contains a base address of  
00000000h with a limit of 3FFh.  
A Fault exception is reported before completion of the  
instruction that generated the exception. By reporting the  
fault before instruction completion, the CPU is left in a  
state that allows the instruction to be restarted and the  
effects of the faulting instruction to be nullified. Fault  
exceptions include divide-by-zero errors, invalid opcodes,  
page faults and coprocessor errors. Debug exceptions  
(vector 1) are also handled as faults (except for data  
breakpoints and single-step operations). After execution  
of the fault service routine, the instruction pointer points to  
the instruction that caused the fault.  
The IDT can be located anywhere in physical memory as  
determined by the IDTR register. The IDT may contain dif-  
ferent types of descriptors: interrupt gates, trap gates and  
task gates. Interrupt gates are used primarily to enter a  
hardware interrupt handler. Trap gates are generally used  
to enter an exception handler or software interrupt han-  
dler. If an interrupt gate is used, the Interrupt Enable Flag  
(IF) in the EFLAGS register is cleared before the interrupt  
handler is entered. Task gates are used to make the tran-  
sition to a new task.  
An Abort exception is a type of fault exception that is  
severe enough that the CPU cannot restart the program at  
the faulting instruction. The double fault (vector 8) is the  
only abort exception that occurs on the CPU.  
Table 3-29. Interrupt Vector Assignments  
3.6.3 Interrupt Vectors  
When the CPU services an interrupt or exception, the cur-  
rent programs instruction pointer and flags are pushed  
onto the stack to allow resumption of execution of the  
interrupted program. In protected mode, the processor  
also saves an error code for some exceptions. Program  
control is then transferred to the interrupt handler (also  
called the interrupt service routine). Upon execution of an  
IRET at the end of the service routine, program execution  
resumes at the instruction pointer address saved on the  
stack when the interrupt was serviced.  
Interrupt  
Vector  
Exception  
Type  
Function  
Divide error  
0
Fault  
Trap/Fault*  
---  
1
Debug exception  
NMI interrupt  
2
3
Breakpoint  
Trap  
4
Interrupt on overflow  
BOUND range exceeded  
Invalid opcode  
Trap  
5
Fault  
Fault  
Fault  
Abort  
---  
6
7
Device not available  
Double fault  
3.6.3.1 Interrupt Vector Assignments  
Each interrupt (except SMI#) and exception are assigned  
one of 256 interrupt vector numbers as shown in Table 3-  
29. The first 32 interrupt vector assignments are defined  
or reserved. INT instructions acting as software interrupts  
may use any of interrupt vectors, 0 through 255.  
8
9
Reserved  
10  
11  
12  
13  
14  
15  
16  
17  
18:31  
32:55  
0:255  
Invalid TSS  
Fault  
Fault  
Fault  
Trap/Fault  
Fault  
---  
Segment not present  
Stack fault  
The non-maskable hardware interrupt (NMI) is assigned  
vector 2. Illegal opcodes including faulty FPU instructions  
will cause an illegal opcode exception, interrupt vector 6.  
NMI interrupts are enabled by setting bit 2 of the CCR7  
register (Index EBh[2] = 1, see Table 3-11 on page 52 for  
register format).  
General protection fault  
Page fault  
Reserved  
FPU error  
Fault  
Fault  
---  
Alignment check exception  
Reserved  
In response to a maskable hardware interrupt (INTR), the  
CPU issues interrupt acknowledge bus cycles used to read  
the vector number from external hardware. These vectors  
should be in the range 32 to 255 as vectors 0 to 31 are pre-  
defined.  
Maskable hardware interrupts  
Programmed interrupt  
Trap  
Trap  
Note: *Data breakpoints and single steps are traps. All other  
debug exceptions are faults.  
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