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30036-23 参数 Datasheet PDF下载

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型号: 30036-23
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内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.5.2.3 Segment Mechanism in Protected Mode  
The segment mechanism in protected mode is more com-  
plex. Basically as in real and virtual 8086 modes the offset  
address is added to the segment base address to pro-  
duce a linear address (Figure 3-5). However, the calcula-  
tion of the segment base address is based on the  
contents of descriptor tables.  
divided in to three fields: the RPL, TI and INDEX fields as  
shown in Figure 3-6 on page 68.  
The segments are assigned permission levels to prevent  
application program errors from disrupting operating pro-  
grams. The Requested Privilege Level (RPL) determines  
the effective privilege level of an instruction. RPL = 0 indi-  
cates the most privileged level, and RPL = 3 indicates the  
least privileged level. Refer to Section 3.9 Protectionon  
page 91.  
If paging is enabled the linear address is further pro-  
cessed by the paging mechanism.  
Descriptor tables hold descriptors that allow management  
of segments and tables in address space while in pro-  
tected mode. The Table Indicator Bit (TI) in the selector  
selects either the General Descriptor Table (GDT) or one  
Local Descriptor Table (LDT). If TI = 0, GDT is selected; if  
TI =1, LDT is selected. The 13-bit INDEX field in the seg-  
ment selector is used to index a GDT or LDT.  
A more detailed look at the segment mechanisms for real  
and virtual 8086 modes and protected modes is illustrated  
in Figure 3-6 on page 68. In protected mode, the segment  
selector is cached. This is illustrated in Figure 3-7 on page  
69.  
3.5.2.4 Segment Selectors  
The segment registers are used to store segment selec-  
tors. In protected mode, the segment selectors are  
32  
Offset Address  
Offset Mechanism  
Linear  
Address  
Physical  
Memory  
Address  
32  
Optional  
Paging Mechanism  
32  
Segment Base  
Address  
32  
Selector Mechanism  
Figure 3-5. Protected Mode Address Calculation  
Revision 1.1  
67  
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