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30036-23 参数 Datasheet PDF下载

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型号: 30036-23
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内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.5.3.3 Task, Gate, Interrupt, and Application and  
System Descriptors  
Besides segment descriptors there are descriptors used  
in task switching, switching between tasks with different  
priority and those used to control interrupt functions:  
The IDT is defined by the Interrupt Descriptor Table Reg-  
ister (IDTR). Some texts refer to this register as an IDT  
descriptor.  
The following instructions are used in conjunction with the  
IDTR:  
Interrupt Descriptors  
Application and System Segment Descriptors  
Gate Descriptors  
LIDT - Load memory to IDTR  
SIDT - Store IDTR to memory  
Task State Segment Descriptors  
The IDTR is set up in real mode using the LIDT instruc-  
tion. This is possible as the LIDT instruction is only one of  
two instructions that directly load a linear address (instead  
of a segment relative address) in protected mode (the  
other instructions is LGDT).  
All descriptors have some things in common. They are all  
eight bytes in length and have three fields (BASE, LIMIT,  
and TYPE). The BASE field defines the starting location  
for the table or segment. The LIMIT field defines the size  
and the TYPE field depends on the type of descriptor.  
One of the main functions of the TYPE field is to define  
the access rights to the associated segment or table.  
As previously shown in Table 3-20 on page 70, the IDTR  
contains a BASE ADDRESS field and a LIMIT field that  
define the IDT tables.  
Interrupt Descriptors  
Application and System Segment Descriptors  
The bit structure and bit definitions for segment descrip-  
tors are shown in Table 3-21 and Table 3-22 on page 72,  
respectively. The explanation of the TYPE field is shown  
in Table 3-23 on page 73.  
The Interrupt Descriptor Table is an array of 256 8-byte (4-  
byte for real mode) interrupt descriptors, each of which is  
used to point to an interrupt service routine. Every inter-  
rupt that may occur in the system must have an associ-  
ated entry in the IDT. The contents of the IDTR are  
completely visible to the programmer through the use of  
the SIDT instruction.  
Table 3-21. Application and System Segment Descriptors  
31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
Memory Offset +4  
9
8
7
6
5
4
3
2
1
0
BASE[31:24]  
G
D
0
A
V
L
LIMIT[19:16]  
P
DPL  
S
TYPE  
BASE[23:16]  
Memory Offset +0  
BASE[15:0]  
LIMIT[15:0]  
Revision 1.1  
71  
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