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30036-23 参数 Datasheet PDF下载

30036-23图片预览
型号: 30036-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.4 ADDRESS SPACES  
The GXLV processor can directly address either memory  
or I/O space. Figure 3-2 illustrates the range of addresses  
available for memory address space and I/O address  
space. For the CPU, the addresses for physical memory  
range between 0000 0000h and FFFFFFFFh (4 GB).  
The accessible I/O address space ranges between  
00000000h and 0000FFFFh (64 KB). The CPU does not  
use coprocessor communication space in upper I/O space  
between 800000F8h and 800000FFh as do the 386-style  
CPUs. The I/O locations 22h and 23h are used for GXLV  
processor configuration register access.  
The configuration registers are modified by writing the  
index of the configuration register to Port 22h, and then  
transferring the data through Port 23h. Accesses to the  
on-chip configuration registers do not generate external  
I/O cycles. However, each operation on Port 23h must be  
preceded by a write to Port 22h with a valid index value.  
Otherwise, subsequent Port 23h operations will communi-  
cate through the I/O port to produce external I/O cycles with-  
out modifying the on-chip configuration registers. Write  
operations to port 22h outside of the CPU index range  
(C0h-CFh and FEh-FFh) result in external I/O cycles and  
do not affect the on-chip configuration registers. Reading  
Port 22h generates external I/O cycles.  
3.4.1 I/O Address Space  
The CPU I/O address space is accessed using IN and  
OUT instructions to addresses referred to as “ports. The  
accessible I/O address space is 64 KB and can be  
accessed as 8-, 16- or 32-bit ports.  
I/O accesses to port address range 3B0h through 3DFh  
can be trapped to SMI by the CPU if this option is enabled  
in the BC_XMAP_1 register (see SMIB, SMIC, and SMID  
bits in Table 4-9 on page 104). Figure 3-2 illustrates the  
I/O address space.  
The GXLV processor configuration registers reside within  
the I/O address space at port addresses 22h and 23h and  
are accessed using the standard IN and OUT instructions.  
Accessible  
Programmed  
I/O Space  
Physical  
Memory Space  
FFFFFFFFh  
FFFFFFFFh  
Not  
Accessible  
Physical Memory  
4 GB  
CPU General  
Configuration  
Register I/O  
0000FFFFh  
Space  
64 KB  
00000023h  
00000022h  
00000000h  
00000000h  
Figure 3-2. Memory and I/O Address Spaces  
Revision 1.1  
63  
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