Processor Programming (Continued)
3.3.3 Model Specific Register Set
3.3.4 Time Stamp Counter
The Model Specific Register (MSR) Set is used to monitor
the performance of the processor or a specific component
within the processor.
The TSC, (MSR[10]), is a 64-bit counter that counts the
internal CPU clock cycles since the last reset. The TSC
uses a continuous CPU core clock and will continue to
count clock cycles unless the processor is in Suspend.
A MSR can be read using the RDMSR instruction, opcode
0F32h. During a MSR read, the contents of the particular
MSR, specified by the ECX register, is loaded into the
EDX:EAX registers.
The TSC is read using a RDMSR instruction, opcode
0F32h, with the ECX register set to 10h. During a TSC
read, the contents of the TSC is loaded into the EDX:EAX
registers.
A MSR can be written using the WRMSR instruction,
opcode 0F30h. During a MSR write, the contents of
EDX:EAX are loaded into the MSR specified in the ECX
register.
The TSC is written to using a WRMSR instruction, opcode
0F30h with the ECX register set to 10h. During a TSC
write, the contents of EDX:EAX are loaded into the TSC.
The RDMSR and WRMSR instructions are privileged
instructions.
The RDMSR and WRMSR instructions are privileged
instructions.
The GXLV processor contains one 64-bit model specific
register (MSR10) the Time Stamp Counter (TSC).
In addition, the TSC can be read using the RDTSC
instruction, opcode 0F31h. The RDTSC instruction loads
the contents of the TSC into EDX:EAX. The use of the
RDTSC instruction is restricted by the TSC flag (bit 2) in
the CR4 register (refer to Tables 3-6 and 3-7 on page 48
for CR4 register information). When the TSC bit = 0, the
RDTSC instruction can be executed at any privilege level.
When the TSC bit = 1, the RDTSC instruction can only be
executed at privilege level 0.
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