Processor Programming (Continued)
The Debug Status Register (DR6) reflects conditions that
were in effect at the time the debug exception occurred.
The contents of the DR6 register are not automatically
cleared by the processor after a debug exception occurs,
and therefore should be cleared by software at the appro-
priate time. Code execution breakpoints may also be gen-
erated by placing the breakpoint instruction (INT3) at the
location where control is to be regained. The single-step
feature may be enabled by setting the TF flag (bit 8) in the
EFLAGS register. This causes the processor to perform a
debug exception after the execution of every instruction.
Table 3-13. DR7 and DR6 Bit Definitions
Number
of Bits
Field(s)
Description
DR7 Register
Debug Control Register (R/W)
R/Wn
2
Applies to the DRn breakpoint address register:
00 = Break on instruction execution only
01 = Break on data write operations only
10 = Not used
11 = Break on data reads or write operations
LENn
2
Applies to the DRn breakpoint address register:
00 = One-byte length
01 = Two-byte length
10 = Not used
11 = Four-byte length
Gn
Ln
1
1
1
If = 1: Breakpoint in DRn is globally enabled for all tasks and is not cleared by the processor as the
result of a task switch.
If = 1: Breakpoint in DRn is locally enabled for the current task and is cleared by the processor as the
result of a task switch.
GD
Global disable of debug register access. GD bit is cleared whenever a debug exception occurs.
DR6 Register
Debug Status Register (RO)
Bn
1
1
1
Bn is set by the processor if the conditions described by DRn, R/Wn, and LENn occurred when the
debug exception occurred, even if the breakpoint is not enabled via the Gn or Ln bits.
BT
BS
BT is set by the processor before entering the debug handler if a task switch has occurred to a task with
the T bit in the TSS set.
BS is set by the processor if the debug exception was triggered by the single-step execution mode (TF
flag, bit 8, in EFLAGS set).
Note: n = 0, 1, 2, and 3
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