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UPD703213YA2 参数 Datasheet PDF下载

UPD703213YA2图片预览
型号: UPD703213YA2
PDF下载: 下载PDF文件 查看货源
内容描述: 32位单芯片微控制器产品 [32-Bit Single-Chip Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 861 页 / 4423 K
品牌: NEC [ NEC ]
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CHAPTER 1 INTRODUCTION  
(h) Watch timer  
This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz)  
or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an  
interval timer.  
(i) Watchdog timer  
Two watchdog timer channels are provided on chip to detect program loops and system abnormalities.  
Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a non-  
maskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs.  
When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an  
overflow occurs.  
Watchdog timer 2 operates by default following reset release.  
It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after  
an overflow occurs.  
(j) Serial interface (SIO)  
The V850ES/KG1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a  
clocked serial interface (CSI0n), a clocked serial interface with an automatic transmit/receive function  
(CSIAn), and an I2C bus interface (I2C0). The µPD703212, 703213, 703214, 703215, 70F3214,  
70F3214H, and 70F3215H can simultaneously use up to six channels, and the µPD703212Y, 703213Y,  
703214Y, 703215Y, 70F3214Y, 70F3214HY, and 70F3215HY up to seven channels.  
For UARTn, data is transferred via the TXDn and RXDn pins.  
For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins.  
For CSIAn, data is transferred via the SOAn, SIAn, and SCKAn pins.  
For I2C0, data is transferred via the SDA0 and SCL0 pins.  
I2C0 is provided only in the µPD703212Y, 703213Y, 703214Y, 703215Y, 70F3214Y, 70F3214HY, and  
70F3215HY.  
Remark n = 0, 1  
(k) A/D converter  
This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is  
performed using the successive approximation method.  
(l) D/A converter  
Two 8-bit resolution D/A converter channels are included on chip. The D/A converter uses the R-2R  
ladder method.  
(m) ROM correction  
This function is used to replace part of a program in the mask ROM with that contained in the internal  
RAM. Up to four correction addresses can be specified.  
(n) Key interrupt function  
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input  
pins.  
38  
User’s Manual U16890EJ1V0UD  
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