CHAPTER 1 INTRODUCTION
1.6 Function Block Configuration
(1) Internal block diagram
NMI
INTC
INTP0 to INTP6
ROM
CPU
Instruction
queue
TI000, TI001, TI010, TI011,
16-bit
PC
Note 1
TI020, TI021, TI030, TI031
timer/event
counter 0: 4 ch
TO00 to TO03
HLDRQ
HLDAK
ASTB
RD
32-bit barrel
shifter
Multiplier
RAM
16 × 16 → 32
16-bit timer/
event counter
PNote 3: 1 ch
TIP00, TIP01Note 3
TOP00, TOP01Note 3
WAIT
System
register
BCU
Note 2
WR0, WR1
CS0, CS1
ALU
8-bit
timer/event
counter 5: 2 ch
General-purpose
registers
TI50, TI51
A0 to A21
AD0 to AD15
32 bits × 32
TO50, TO51
ROM
correction
8-bit timer H:
2 ch
TOH0, TOH1
SO00, SO01
SI00, SI01
SCK00, SCK01
CSI0: 2 ch
CSIA: 2 ch
CLKOUT
X1
Port
D/A
A/D
converter converter
PLL
CG
X2
SOA0, SOA1
SIA0, SIA1
XT1
SCKA0, SCKA1
XT2
RESET
SDA0Note 4
SCL0Note 4
I2CNote 4
: 1 ch
TXD0, TXD1
RXD0, RXD1
ASCK0
Regulator
VDD
UART: 2 ch
V
PPNote 5/ICNote 5/FLMD0Note 5
FLMD1Note 5
Key interrupt
function
Watchdog
timer: 2 ch
BVDD
KR0 to KR7
BVSS
EVDD
Watch timer
RTP00 to RTP05
RTO: 1 ch
EVSS
VSS
Notes 1. µPD703212, 703212Y:
µPD703213, 703213Y:
64 KB (mask ROM)
96 KB (mask ROM)
128 KB (mask ROM)
256 KB (mask ROM)
µPD703214, 703214Y:
µPD703215, 703215Y:
µPD70F3214, 70F3214Y, 70F3214H, 70F3214HY: 128 KB (flash memory)
µPD70F3215H, 70F3215HY:
256 KB (flash memory)
4 KB
2. µPD703212, 703212Y, 703213, 703213Y:
µPD703214, 703214Y, 70F3214, 70F3214Y, 70F3214H, 70F3214HY: 6 KB
µPD703215, 703215Y, 70F3215H, 70F3215HY:
16 KB
3. Only in the µPD703215, 703215Y, 70F3215H, 70F3215HY
4. Only in the µPD703212Y, 703213Y, 703214Y, 703215Y, 70F3214Y, 70F3214HY, 70F3215HY
5. IC:
VPP:
µPD703212, 703212Y, 703213, 703213Y, 703214, 703214Y, 703215, 703215Y
µPD70F3214, 70F3214Y
FLMD0, FLMD1: µPD70F3214H, 70F3214HY, 70F3215H, 70F3215HY
36
User’s Manual U16890EJ1V0UD
NEC [ NEC ]
