µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
4. CPU FUNCTIONS
{ RISC-based architecture
{ Uses five-stage pipeline control to enable single-clock execution of almost all instructions
{ Minimum instruction execution time 25 ns (@ 40-MHz operation) ... µPD703100A-40
30 ns (@ 33-MHz operation) ... µPD703100A-33, 703101A-33, 703102A-33
Program space: 64-Mbyte linear
Data space: 4-Gbyte linear
{ Memory space
{ General registers 32 bits × 32
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiply/divide instructions
{ Saturated operation instructions
{ 32-bit shift instruction: 1 clock
{ Long/short format
{ Four types of bit manipulation instructions
•
•
•
•
Set
Clear
Not
Test
5. BUS CONTROL FUNCTIONS
{ 16-bit/8-bit data bus sizing function
{ 8-space chip select output function
{ Wait functions
•
•
Programmable wait function for up to seven states for each memory block
External wait function using WAIT pin
{ Idle state insertion function
{ Bus mastering arbitration function
{ Bus hold function
{ Alternate function port pins are connectable to external bus
23
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
