µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
6.3 DRAM Controller
6.3.1 Features
{ Generates the RAS, UCAS, and LCAS signals
{ Can be connected directly to high-speed page DRAM and EDO DRAM
{ Supports RAS hold mode
{ Can assign 4 types of DRAM to 8 memory block space
{ Supports 2CAS type DRAM
{ Can be switched between row and column address multiplex widths
{ Can insert waits (0 to 3 waits) at each of the following timings
•
•
•
•
Row address pre-charge wait
Row address hold wait
Data access wait
Column address pre-charge wait
{ Supports CBR refresh and CBR self refresh
6.3.2 DRAM connections
The following figure shows DRAM connection examples.
Figure 6-3. DRAM Connection Examples (1/2)
(a) 16-Mbit (1 M × 16) DRAM
A0 to A9
A1 to A10
D0 to D15
I/O1 to I/O16
RAS
LCAS
UCAS
WE
RASn
LCAS
UCAS
WE
OE
OE
V850E/MS1
16-Mbit (1 M × 16) DRAM
Remark n = 0 to 7
27
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
