µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
3. FUNCTION BLOCKS
3.1 Internal Units
3.1.1 CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits, or 32 bits × 32 bits → 64
bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
3.1.2 Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from the external memory area and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in the
internal instruction queue of the CPU.
The BCU contains a DRAM controller (DRAMC), page ROM controller, and DMA controller (DMAC).
(a) DRAM controller (DRAMC)
The DRAM controller generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to the
DRAM.
It supports high-speed page DRAM and EDO DRAM, and has two types of cycles for accessing DRAM.
These types of cycles are referred to as normal access (off-page) and page access (on-page).
The DRAM controller also has a refresh function that is associated with the CBR refresh cycle.
(b) Page ROM controller
The page ROM controller supports access to ROM that has the page access function.
It compares the address with that of the preceding bus cycle and controls the waits for normal access (off-
page) and page access (on-page). The page ROM controller can support page sizes of 8 to 64 bytes.
(c) DMA controller (DMAC)
The DMA controller transfers data between memory and an I/O device in place of the CPU.
The two address modes are flyby (one-cycle) transfer and two-cycle transfer. The three bus modes are single
transfer, single-step transfer, and block transfer.
3.1.3 ROM
The µPD703101A-33 contains 96 Kbytes of mask ROM, and the µPD703102A-33 contains 128 Kbytes of mask
ROM.
The CPU can access ROM in one clock cycle when an instruction is fetched.
When single-chip mode 0 is set, ROM is mapped to the address space starting at 00000000H. When single-chip
mode 1 is set, ROM is mapped to the address space starting at 00100000H. When ROM-less mode 0 or 1 is set,
ROM cannot be accessed.
The µPD703100A-33 and µPD703100A-40 have no internal ROM.
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Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
