µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(3/4)
Pin Name
LCAS
I/O
O
Function
Alternate Function
P90/LWR
Column address strobe signal output for DRAM’s lower data
Column address strobe signal output for DRAM’s higher data
Low address strobe signal output for DRAM
UCAS
O
P91/UWR
RAS0 to RAS3
RAS4
O
P80/CS0 to P83/CS3
P84/CS4/IOWR
P85/CS5/IORD
P86/CS6
RAS5
RAS6
RAS7
P87/CS7
BCYST
CS0 to CS3
O
O
Strobe signal output indicating start of bus cycle
Chip select signal output
P94
P80/RAS0 to
P83/RAS3
CS4
P84/RAS4/IOWR
P85/RAS5/IORD
P86/RAS6
CS5
CS6
CS7
P87/RAS7
WAIT
REFRQ
IOWR
IORD
I
Control signal input for inserting waits in bus cycle
Refresh request signal output for DRAM
DMA write strobe signal output
PX6
O
O
O
I
PX5
P84/RAS4/CS4
P85/RAS5/CS5
DMA read strobe signal output
DMARQ0 to
DMARQ3
DMA request signal input
P04/INTP100 to
P07/INTP103
DMAAK0 to
DMAAK3
O
O
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
TC0 to TC3
DMA end (terminal count) signal output
P104/INTP120 to
P107/INTP123
HLDAK
HLDRQ
ANI0 to ANI7
NMI
O
I
Bus hold acknowledge output
Bus hold request input
P96
P97
I
Analog input to A/D converter
Non-maskable interrupt request input
System clock output
P70 to P77
P20
I
CLKOUT
CKSEL
O
I
PX7
—
Input for specifying clock generator’s operation mode
Specify operation modes
MODE0 to
MODE3
I
—
RESET
X1
I
I
System reset input
—
Oscillator connection for system clock. Input is via X1 when using an
external clock.
—
X2
—
I
—
ADTRG
AVREF
AVDD
AVSS
A/D converter external trigger input
Reference voltage input for A/D converter
Positive power supply for A/D converter
Ground potential for A/D converter
P127/INTP153
I
—
—
—
—
—
16
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
