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UPD43256BCZ-70LL 参数 Datasheet PDF下载

UPD43256BCZ-70LL图片预览
型号: UPD43256BCZ-70LL
PDF下载: 下载PDF文件 查看货源
内容描述: 256K - BIT的CMOS静态RAM的32K字×8位 [256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 24 页 / 174 K
品牌: NEC [ NEC ]
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µPD43256B  
Write Cycle Timing Chart 1 (WE Controlled)  
t
WC  
Address (Input)  
CS (Input)  
t
CW  
t
AW  
t
AS  
t
WP  
t
WR  
WE (Input)  
t
OW  
t
WHZ  
t
DW  
t
DH  
High  
High  
I/O (Input/Output)  
Indefinite data out  
Data in  
Indefinite data out  
impe-  
dance  
impe-  
dance  
Cautions 1. CS or WE should be fixed to high level during address transition.  
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite  
in phase with output signals.  
Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE.  
2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level,  
read operation is executed. Therefore OE should be at high level to make the I/O pins high  
impedance.  
3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins  
will remain high impedance state.  
13  
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