CHAPTER 9 WATCHDOG TIMER
9.4 Watchdog Timer Operation
9.4.1 Operation as watchdog timer
The watchdog timer detects a program runaway when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0
to WDCS2) of watchdog timer clock select register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the watchdog
timer is started. Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been
started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the
runaway detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on
the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1
to clear the watchdog timer before executing the STOP instruction.
Cautions 1. The actual runaway detection time may be up to 0.8% shorter than the set time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer count
operation is stopped. Even when the main system clock continues oscillating in this case,
watchdog timer count operation is stopped.
Table 9-4. Watchdog Timer Runaway Detection Time
WDCS2 WDCS1 WDCS0
Runaway Detection Time
11 × 1/fX
At fX = 5.0 MHz
410 µs
0
0
1
1
0
1
0
1
0
0
0
0
2
2
2
2
13 × 1/fX
15 × 1/fX
17 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
User’s Manual U15075EJ1V0UM00
181
NEC [ NEC ]
