CHAPTER 9 WATCHDOG TIMER
9.3 Watchdog Timer Control Registers
The watchdog timer is controlled by the following two registers.
•
•
Watchdog timer clock select register (WDCS)
Watchdog timer mode register (WDTM)
(1) Watchdog timer clock select register (WDCS)
This register sets the watchdog timer count clock.
WDCS is set with an 8-bit memory manipulation instruction.
RESET input sets WDCS to 00H.
Figure 9-2. Format of Watchdog Timer Clock Select Register
Symbol
WDCS
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF42H
After reset
00H
R/W
R/W
WDCS2 WDCS1 WDCS0
WDCS2 WDCS1 WDCS0
Interval
Watchdog timer count clock selection
/24 (312.5 kHz)
211/f
213/f
215/f
217/f
X
X
X
X
(410 µs)
fX
fX
fX
fX
0
0
1
1
0
0
0
0
0
1
/26 (78.1 kHz)
(1.64 ms)
(6.55 ms)
(26.2 ms)
0
/28 (19.5 kHz)
1
/210 (4.88 kHz)
Other than above
Setting prohibited
Remarks 1. fX : Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
User’s Manual U15075EJ1V0UM00
179
NEC [ NEC ]
