CHAPTER 9 WATCHDOG TIMER
(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WDTM to 00H.
Figure 9-3. Format of Watchdog Timer Mode Register
Symbol
WDTM
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address
FFF9H
After reset
00H
R/W
R/W
RUN
WDTM4 WDTM3
Watchdog timer operation selectionNote 1
RUN
0
1
Stops counting.
Clears counter and starts counting.
Watchdog timer operation mode selectionNote 2
WDTM4 WDTM3
0
0
1
1
0
1
0
1
Operation stop
Interval timer mode (Generates a maskable interrupt upon overflow occurrence.)Note 3
Watchdog timer mode 1 (Generates a non-maskable interrupt upon overflow occurrence.)
Watchdog timer mode 2 (Starts reset operation upon overflow occurrence.)
Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operation as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the watchdog timer clock select register (WDCS).
2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of the
interrupt request flag register 0 (IF0)) is set to 0. When watchdog timer mode 1 or 2 is
selected with TMIF4 set to 1, a non-maskable interrupt is generated upon the
completion of rewriting WDTM4.
User’s Manual U15075EJ1V0UM00
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NEC [ NEC ]
