DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
Dynamic ODT: Behavior with ODT pin being asserted together with write command
for the duration of 4 clock cycles.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK#
ODTLcnw
CMD
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
ODT
ODTH4
tAONmin
ODTLoff
RTT_WR
tAOFmin
RTT
tAONmax
tAOFmax
ODTLon
ODTLcwn4
DQS/DQS
WL
Din
n
Din
n+1
Din
n+2
Din
n+3
DQ
Do not
care
Transitioning
Version 2.3
02/2017
80
Nanya Technology Cooperation ©
All Rights Reserved.