DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
Latencies and timing parameters relevant for Dynamic ODT
Definition for all
DDR3(L) speed pin
Name and Description
Abbr.
Defined from
Defined to
Unit
tCK
registering external
ODT signal high
ODT turn-on Latency
ODTLon
turning termination on
ODTLon=WL-2
ODTLoff=WL-2
ODTLcnw=WL-2
ODTLcwn4=4+ODTLoff
ODTLcwn8=6+ODTLoff
ODTH4=4
registering external
ODT signal low
ODT turn-off Latency
ODTLoff
ODTLcnw
ODTLcwn4
ODTLcwn8
ODTH4
turning termination off
tCK
ODT Latency for changing from
RTT_Nom to RTT_WR
registering external
write command
change RTT strength from
RTT_Nom to RTT_WR
tCK
ODT Latency for change from
RTT_WR to RTT_Nom (BL=4)
registering external
write command
change RTT strength from
RTT_WR to RTT_Nom
tCK
ODT Latency for change from
RTT_WR to RTT_Nom (BL=8)
registering external
write command
change RTT strength from
RTT_WR to RTT_Nom
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Minimum ODT high time
after ODT assertion
registering ODT high ODT registered low
Minimum ODT high time
after Write (BL=4)
registering write with
ODT registered low
ODT high
ODTH4
ODTH4=4
Minimum ODT high time
after Write (BL=8)
registering write with
ODT register low
ODT high
ODTH8
ODTH8=6
ODTLcnw
RTT valid
ODTLcwn
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
RTT change skew
tADC
Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
Version 2.3
02/2017
77
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