DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
ODT during Reads:
As the DDR3(L) SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle
before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble
as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM
stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM
complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read
than shown in this example.
ODT must be disabled externally during Reads by driving ODT low. (Example: CL=6;
AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
CK
CK
CMD
Read
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
ODT
RL = AL + CL
ODTLon = CWL + AL - 2
ODTLoff = CWL + AL - 2
RTTR_TNTOM
tAONmax
tAOFmin
DRAM
ODT
RTT_NOM
tAOFmax
DQSdiff
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
DQ
Version 2.3
02/2017
75
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