NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3(L) SDRAM that allows the DRAM to turn on/off termination resistance
for each DQ, DQS, , and DM for x8 configuration (and TDQS, T for x8 configuration, when enabled via A11=1 in
MR1) via the ODT control pin. For x16 configuration, ODT is applied to each DQ, DQSU, U, DQSL, L, DMU and
DMl signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by
allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown as below.
Functional Representation of ODT
ODT
/ 2
VDDQ
To other
circuitry
like
RTT
Switch
RCV, ...
DQ , DQS, DM, TDQS
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The
value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1
and MR2 are programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is
determined by the settings of those bits.
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
DRAM does not use any write or read command decode information.
Termination Truth Table
ODT pin
DRAM Termination State
OFF
0
1
ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general)
Version 1.4
05/2019
67
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