NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
DM:stable at 0;
Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
Active Power-Down Current
CKE: Low; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: stable at 1;
Command, Address, Bank Address Inputs: stable at 0;
Data IO: MID-LEVEL;
IDD3P
DM:stable at 0;
Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1,7); AL: 0;
: High between RD;
Command, Address, Bank Address Inputs: partially toggling;
IDD4R
Data IO: seamless read data burst with different data between one burst and the next one;
DM:stable at 0;
Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
Operating Burst Write Current
CKE: High; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: High between WR;
Command, Address, Bank Address Inputs: partially toggling;
Data IO: seamless write data burst with different data between one burst and the next one ;
DM: stable at 0;
IDD4W
Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at HIGH;
Version 1.4
05/2019
123
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