MUPA64K16 Alto Priority Queue Scheduler
Table 13: Pipeline Instructions
Pipeline
Cycle
Clock Operation
Cycle
Instruction OP[2:0] REG[2:0] /W PQ[3:0]
P
1
Read UGR, Start UID Get (9
UID Get
5
5
1
N
clocks)
P-1
P-1
P-1
P
4
Wait for Both to complete
Read MDR
7
Noop
Noop
0
0
0
3
6
1
0
0
1
6
1
1
0
0
0
N/A
N/A
N/A
N
10
13
15
17
Read MKR (if desired)
Write IKR
Noop
P
Write IDR, start Both (10 clocks)
Both
P-1
Write UPR, Start UID Put (3
clocks
UID Put
N/A
P+1
P
19
22
25
28
31
33
35
Read UGR, Start UID Get
Wait for Both to complete
Read MDR
UID Get
5
5
1
N
P
Noop
Noop
0
0
0
3
6
1
0
0
1
6
1
1
0
0
0
N/A
N/A
N/A
N
P
Read MKR (if desired)
Write IKR
P+1
P+1
P
Noop
Write IDR, start Both (10 clocks)
Write UPR, Start UID Put
Both
UID Put
N/A
JTAG INTERFACE
TCLK (JTAG Test Clock, Input)
TCLK is the Test Clock input.
This section contains the Test Access Port and
Boundary Scan Architecture as specified by the IEEE
JTAG standard 1149.1. It consists of five JTAG
interface signals TCK, TMS, /TRST, TDI and TDO.
TMS (JTAG Test Mode Select, Input)
TMS is the Test Mode Select input.
TDI (JTAG Test Data Input, Input)
TDI is the Test Data input.
/TRST (JTAG Reset, Input)
/TRST is the Test Reset input.
TDO (JTAG Test Data Output, Output)
TDO is the Test Data output.
MUSIC Semiconductors Confidential
12
Rev 0.3 Draft
MUSIC [ MUSIC SEMICONDUCTORS ]
