MUPA64K16 Alto Priority Queue Scheduler
Table 10: UID Get Operation
Operation
Instruction OP[2:0] REG[2:0] /W PQ[3:0]
Start
Get
UID
UID Get
5
N/A
1
N
Wait for UID
Get
to
complete
Read UGR
Noop
0
5
1
N
Table 11: UID Put Operation
Instruction OP[2:0] REG[2:0] /W PQ[3:0]
Operation
Write UPR,
Start UID
Put
UID Put
6
6
0
N
Table 12: Size and Wrap Registers
MR[2:0]
Number of Number of Number of
Width of
PQ Lines
Queues
Size
Wrap registers
Size register used
Registers
000
001
010
011
1
2
1
1
2
16 bits
15 bits
14 bits
13 bits
12 bits
none
2
4
PQ[0]
4
4
PQ[1,0]
PQ[2:0]
PQ[3:0]
8
8
8
100, 101,
110, 111
16
16
16
Size and Wrap register bank and instruction
decode
for wrap register, using PQ value and mode register
contents, appropriate wrap register is updated from
DQ input.
The SWM module contains: Instruction decode and
write logic for 16 SR (Size) registers and 16 WR
(Wrap) registers. Priority queue can be configured
with use of PQ[3:0] inputs and mode register bits
MR[2:0]. Table 12 shows the relationship between
the PQ[3:0], MR[2:0] and number of queues.
When an instruction that operates on queue (insert,
extract, peek, both) is detected, PQ, opcode, size
register, wrap register, IKR and IDR are stored in a
buffer. Upon detection of completion of previously
issued queue instruction, the contents are
transferred to the priority queue for execution of the
queue instruction. The buffer is now ready to accept
one additional queue instruction from external
interface.
Decode logic for queue operation instructions: insert,
extract, both, peek, Ram Write, Ram Read. Decode
logic for instruction that reads size and wrap register
contents pointed to by PQ inputs.
Size register contents are cleared when a write is
detected either for mode register or for size register.
Size register contents pointed to by PQ and mode
register are increased or decreased by one if an
instruction in execution is insert or extract.
If it is not required to read the Size Register all the
time, it can be tracked in ASIC.
The following is an example of a complex set of
pipelined instructions. The basic sequence is six
instructions, but they're interleaved to achieve
optimal pipelining.
Wrap register contents are cleared when a write is
detected for mode register. When a write is detected
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