Timing Diagrams
MU9C8338A 10/100Mb Ethernet Filter Interface
Capacitance
Symbol
Parameter
Typ
Units
Notes
C
Input Capacitance
6
pF
f = 1 MHz, V = 0 V
IN
IN
C
Output Capacitance
Bi-directional Capacitance
9
pF
pF
f = 1 MHz, V = 0 V
OUT
OUT
C
10
f = 1 MHz, V = 0 V
I0
I0
TIMING DIAGRAMS
Host Processor
Table 33: Host Processor Interface Timing Data
No.
1
Symbol
tPLDX
Parameter (ns)
Min
Max
Notes
/PCS (/PCSS) LOW to D(15:0) enable
/PCS (/PCSS) HIGH to D(15:0) disable
/WRITE setup to /PCS (/PCSS)
/WRITE hold from /PCS (/PCSS)
SYSCLK HIGH to D(15:0) (read)
D(15:0) setup to /PCS (/PCSS) HIGH (write)
D(15:0) hold from /PCS (/PCSS) HIGH (write)
PROC_RDY delay from SYSCLK HIGH
A(7:0) setup to /PCS (/PCSS) LOW
A(7:0) hold from /PCS (/PCSS) LOW
/PCS (/PCSS) HIGH time
SYSCLK+5
SYSCLK+5
2
tPHDZ
tWVPL
tPLWX
tCHDV
tDVPH
tPHDX
tCHPRH
tAVPL
3
3
3
4
5
10
10
6
5
3
7
8
9
5
10
11
12
13
tPLAX
3
tPHPL
2*SYSCLK+8
10
tPLPRL
tPRHPRL
/PCS (/PCSS) to PROC_RDY LOW
PROC_RDY HIGH time
1*SYSCLK
t3
t9
t11
/PCS (/PCSS)
D[15:0](read)
t1
t5
t2
t10
t4
A[7:0]
/WRITE (read)
t8
t12
t13
PROC_RDY
SYSCLK
Figure 7: Host Processor Interface - Read Sequence
Rev. 0a
23
MUSIC [ MUSIC SEMICONDUCTORS ]
