Timing Diagrams
MU9C8338A 10/100Mb Ethernet Filter Interface
Table 40: Tag Ports TP_DV and TP_SD Timing Data
No.
50
51
52
53
Symbol
tRCJTOH
tRCHTSH
tRCHTDL
tRCHTSL
Parameter (ns)
Min
0
Max
20
Notes
Delay RX_CLK HIGH to TP_DV HIGH
Delay RX_CLK HIGH to TP_SD HIGH
Delay RX_CLK HIGH to TP_DV LOW
Delay RX_CLK HIGH to TP_SD LOW
0
20
0
20
0
20
RX_CLK
50
52
TP_DV
TP_SD
51
53
BIT0
BIT5
(MSB)
BIT4
BIT3
BIT2
BIT1
(LSB)
Timing Data for LANCAM Interface
Switching Characteristics
LANCAM Compare Cycle Time
70 ns
Typ
90 ns
Typ
120 ns (90 ns)
Typ
No.
Symbol
Parameter
Notes
1
tELEL
Chip Enable Compare Cycle Time
Chip Enable LOW Pulse Width
Chip Enable HIGH Pulse Width
7*SYSCLK 8*SYSCLK
1*SYSCLK 2*SYSCLK
2*SYSCLK 3*SYSCLK
3*SYSCLK 4*SYSCLK
1*SYSCLK 1*SYSCLK
4*SYSCLK 4*SYSCLK
3*SYSCLK 4*SYSCLK
8*SYSCLK
2*SYSCLK
4*SYSCLK
5*SYSCLK
1*SYSCLK
4*SYSCLK
5*SYSCLK
1
Short Cycle
Medium Cycle
Long Cycle
1,2
2
tELEH
3
4
5
tEHEL
tEHELC
tELQV
1
1
Chip Enable HIGH Pulse Width (Compare)
Chip Enable LOW to DQ Bus VALID (Read)
1,3
All
No.
Symbol
tKHEL
Parameter (all times in nanoseconds)
Min.
5
Max.
19
Notes
6
7
SYSCLK HIGH to Chip Enable LOW Delay Time
SYSCLK HIGH to Chip Enable HIGH Delay Time
SYSCLK HIGH to CAM Controls INVALID Delay Time
SYSCLK HIGH to CAM Controls VALID Delay Time
SYSCLK HIGH to DQ Bus VALID Delay Time
SYSCLK HIGH to DQ Bus INVALID Delay Time
Full Input VALID to SYSCLK HIGH Setup Time
MATCH Input VALID to SYSCLK HIGH Setup Time
tKHEH
tKHGX
tKHGV
tKHQV
tKHQX
tFIVKH
tMIVKH
5
19
8
5
19
4
4
9
5
19
10
5
19
11
5
19
12
10
5
5
6
13
Notes:
1.
2.
3.
The MU9C8338A LANCAM interface must be configured to accept the speed grade of the LANCAM being used. Once it is configured for the
appropriate speed grade (70 ns, 90 ns, or 120 ns (90 ns)) the cycle time will vary accordingly.
The MU9C8338A contains built-in routines that include LANCAM short, medium, or long cycles. The cycle will vary depending upon what
LANCAM cycle is being performed by the MU9C8338A.
A LANCAM read cycle initiated by the MU9C8338A could be to the internal memory array or to the LANCAM registers. The timing specified
meets the requirements to successfully read from either source.
4.
5.
6.
CAM Control signals are /CM, /W, and /EC.
The /FI input is latched by the MU9C8338A on every rising edge of SYSCLK.
The LANCAM interface is designed to work properly with up to four LANCAMs.
Rev. 0a
27
MUSIC [ MUSIC SEMICONDUCTORS ]
